r1153 - in trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian: . patches
Sven Luther
luther@haydn.debian.org
Mon, 16 Aug 2004 09:50:26 -0600
Author: luther
Date: 2004-08-16 09:50:22 -0600 (Mon, 16 Aug 2004)
New Revision: 1153
Added:
trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/patches/powerpc-g4-l2-flush-errata.dpatch
Modified:
trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/changelog
Log:
Added powerpc g4 l2 flush errata dpatch, and added changelog entry for the marvell fix hch is working on.
Modified: trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/changelog
===================================================================
--- trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/changelog 2004-08-16 15:16:24 UTC (rev 1152)
+++ trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/changelog 2004-08-16 15:50:22 UTC (rev 1153)
@@ -1,8 +1,11 @@
kernel-source-2.6.8 (2.6.8-2) UNRELEASED; urgency=high
* Add updated fix for generic UP kernel builds on IA64 (dann frazier).
+ * Added g4 l2 flush and MSR patch from Jacob Pan (Sven Luther).
+ * Added marvell gigabit ethernet driver errata patch from Nicolas Det
+ (Sven Luther).
- -- dann frazier <dannf@debian.org> Mon, 16 Aug 2004 09:07:36 -0600
+ -- Sven Luther <luther@debian.org> Mon, 16 Aug 2004 17:46:29 +0200
kernel-source-2.6.8 (2.6.8-1) unstable; urgency=high
Added: trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/patches/powerpc-g4-l2-flush-errata.dpatch
===================================================================
--- trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/patches/powerpc-g4-l2-flush-errata.dpatch 2004-08-16 15:16:24 UTC (rev 1152)
+++ trunk/kernel/source/kernel-source-2.6.8-2.6.8/debian/patches/powerpc-g4-l2-flush-errata.dpatch 2004-08-16 15:50:22 UTC (rev 1153)
@@ -0,0 +1,239 @@
+#! /bin/sh -e
+##
+## All lines beginning with `## DP:' are a description of the patch.
+## DP: Description: Fixes g4 l2 cache flush and MSR erratas.
+## DP: Patch author: Sven Luther <luther@debian.org>
+## DP: Upstream status: under review by benh.
+
+. $(dirname $0)/DPATCH
+
+@DPATCH@
+diff -urN -X dontdiff linux-2.6.7-pegasos-orig/arch/ppc/kernel/cputable.c linux-2.6.7/arch/ppc/kernel/cputable.c
+--- linux-2.6.7-pegasos-orig/arch/ppc/kernel/cputable.c 2004-08-11 23:19:46.000000000 -0600
++++ linux-2.6.7/arch/ppc/kernel/cputable.c 2004-08-12 20:08:49.000000000 -0600
+@@ -263,7 +263,8 @@
+ CPU_FTR_COMMON |
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -274,7 +275,8 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -285,7 +287,7 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_NEED_COHERENT,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -296,7 +298,7 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
+- CPU_FTR_NEED_COHERENT,
++ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -307,7 +309,8 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
++ CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -318,7 +321,7 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -329,7 +332,8 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
++ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -340,7 +344,8 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
++ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
++ CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -351,7 +356,7 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+@@ -362,7 +367,7 @@
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
+ CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
+- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
++ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
+ COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
+ 32, 32,
+ __setup_cpu_745x
+diff -urN -X dontdiff linux-2.6.7-pegasos-orig/arch/ppc/kernel/l2cr.S linux-2.6.7/arch/ppc/kernel/l2cr.S
+--- linux-2.6.7-pegasos-orig/arch/ppc/kernel/l2cr.S 2004-08-12 02:31:16.000000000 -0600
++++ linux-2.6.7/arch/ppc/kernel/l2cr.S 2004-08-12 20:52:04.716349536 -0600
+@@ -36,7 +36,9 @@
+ several months. The L2CR is similar, but I'm going
+ to assume the user of this functions knows what they
+ are doing.
+-
++ June 17, 2004.
++ - JPAN: Fixed 745X L3 cache enablement routine, also use HW flush assist.
++
+ Author: Terry Greeniaus (tgree@phys.ualberta.ca)
+ Please e-mail updates to this file to me, thanks!
+ */
+@@ -154,9 +156,7 @@
+ Don't do this unless you accomodate all processor variations.
+ The bit moved on the 7450.....
+ ****/
+-
+- /* TODO: use HW flush assist when available */
+-
++BEGIN_FTR_SECTION
+ lis r4,0x0002
+ mtctr r4
+ li r4,0
+@@ -175,7 +175,23 @@
+ dcbf 0,r4
+ addi r4,r4,32 /* Go to start of next cache line */
+ bdnz 1b
++END_FTR_SECTION_IFCLR(CPU_FTR_HWFLUSH_L2_CACHE)
+
++BEGIN_FTR_SECTION
++ /* Use HW flush assist, MPC7447A errata #3 */
++ oris r4,r4,0x0010 /* Set L2CR[IONLY/11] = 1 */
++ oris r4,r4,0x0001 /* Set L2CR[DONLY/15] = 1 */
++ mtspr L2CR,r4 /* Lock the L2 */
++ sync
++ ori r4,r4,0x0800 /* Set L2CR[L2HWF/20] = 1 */
++ mtspr L2CR,r4 /* Flush the L2 */
++1:
++ mfspr r4,L2CR
++ andi. r4,r4,0x0800 /* L2HWF still set? */
++ bne 1b
++ sync /* sync to clear the store queues before L3 flush (UM step 5)*/
++END_FTR_SECTION_IFSET(CPU_FTR_HWFLUSH_L2_CACHE)
++
+ 2:
+ /* Set up the L2CR configuration bits (and switch L2 off) */
+ /* CPU errata: Make sure the mtspr below is already in the
+@@ -292,17 +308,18 @@
+
+ /* Flush the cache.
+ */
+-
+- /* TODO: use HW flush assist */
+-
+- lis r4,0x0008
+- mtctr r4
+- li r4,0
+-1:
+- lwzx r0,r0,r4
+- dcbf 0,r4
+- addi r4,r4,32 /* Go to start of next cache line */
+- bdnz 1b
++ /* use HW flush assist. (UM 3.6.3.1.5) */
++ mfspr r4, SPRN_L3CR
++ oris r4,r4,0x0040 /* Set L3CR[L3IO/9] = 1. */
++ ori r4,r4,0x0040 /* Set L3CR[L3DO/29] = 1.*/
++ mtspr 1018,r4 /* Lock the L3 by making IONLY and DONLY */
++ ori r4,r4,0x0800 /* Set L3CR[L3HWF/20] for hardware flush */
++ mtspr SPRN_L3CR,r4
++flush_745x_L3_poll:
++ mfspr r4,SPRN_L3CR
++ rlwinm. r4,r4,0,20,20
++ bne flush_745x_L3_poll
++ sync /* Clear the store queues per procedure (UM step 8) */
+
+ 2:
+ /* Set up the L3CR configuration bits (and switch L3 off) */
+@@ -348,8 +365,8 @@
+ cmplwi r5,0
+ beq 4f
+
+- /* Enable the cache */
+- oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
++ /* enable L3 clock */
++ oris r3,r3,(L3CR_L3CLKEN)@h
+ mtspr SPRN_L3CR,r3
+ sync
+
+@@ -357,6 +374,15 @@
+ li r0,256
+ mtctr r0
+ 1: bdnz 1b
++
++ /* Clear MSSSR0 which may cause parity error */
++ xor r5,r5,r5
++ mtspr 1015, r5
++
++ /* Enable L3 cache */
++ oris r3,r3,(L3CR_L3E)@h
++ mtspr SPRN_L3CR,r3
++ sync
+
+ /* Restore MSR (restores EE and DR bits to original state) */
+ 4: SYNC
+diff -urN -X dontdiff linux-2.6.7-pegasos-orig/arch/ppc/kernel/traps.c linux-2.6.7/arch/ppc/kernel/traps.c
+--- linux-2.6.7-pegasos-orig/arch/ppc/kernel/traps.c 2004-08-12 02:31:30.000000000 -0600
++++ linux-2.6.7/arch/ppc/kernel/traps.c 2004-08-12 02:10:05.000000000 -0600
+@@ -263,7 +263,9 @@
+ case 0x80000:
+ printk("Machine check signal\n");
+ break;
+- case 0: /* for 601 */
++ case 0: /* for 601 and 744x */
++ printk("Transfer error ack signal if 601, or MCP if 744x \n");
++ break;
+ case 0x40000:
+ case 0x140000: /* 7450 MSS error and TEA */
+ printk("Transfer error ack signal\n");
+diff -urN -X dontdiff linux-2.6.7-pegasos-orig/include/asm-ppc/cputable.h linux-2.6.7/include/asm-ppc/cputable.h
+--- linux-2.6.7-pegasos-orig/include/asm-ppc/cputable.h 2004-08-11 23:19:46.000000000 -0600
++++ linux-2.6.7/include/asm-ppc/cputable.h 2004-08-12 19:51:45.000000000 -0600
+@@ -77,6 +77,7 @@
+ #define CPU_FTR_HAS_HIGH_BATS 0x00010000
+ #define CPU_FTR_NEED_COHERENT 0x00020000
+ #define CPU_FTR_NO_BTIC 0x00040000
++#define CPU_FTR_HWFLUSH_L2_CACHE 0x00080000
+
+ #ifdef __ASSEMBLY__
+