Bug#479529: cacao_0.99~rc3-1(mips/experimental): FTBFS: Error: opcode not supported on this processor
Thiemo Seufer
ths at networkno.de
Mon May 5 16:49:41 UTC 2008
Frank Lichtenheld wrote:
> On Mon, May 05, 2008 at 01:44:21PM +0200, Michael Koch wrote:
> > On Mon, May 05, 2008 at 12:45:57PM +0200, Frank Lichtenheld wrote:
> > > | cc -I../../../../src -I../../../.. -I../../../../src -D__MIPS__ -D__LINUX__ -ansi -pedantic -Wall -Wno-long-long -D_POSIX_C_SOURCE=199506L -D_XOPEN_SOURCE=500 -D_XOPEN_SOURCE_EXTENDED -D_BSD_SOURCE -g -O2 -g -Wall -O2 -c asmpart.S -fPIC -DPIC -o .libs/asmpart.o
> > > | asmpart.S: Assembler messages:
> > > | asmpart.S:166: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f12,4*8($8)'
> > > | asmpart.S:167: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f14,5*8($8)'
> > > | asmpart.S:241: Warning: No .cprestore pseudo-op used in PIC code
> > > | asmpart.S:280: Warning: No .cprestore pseudo-op used in PIC code
> > > | asmpart.S:305: Error: opcode not supported on this processor: mips1 (mips1) `sdc1 $f12,(4+(0))*4($29)'
> > > | asmpart.S:305: Error: opcode not supported on this processor: mips1 (mips1) `sdc1 $f14,(6+(0))*4($29)'
> > > | asmpart.S:306: Error: opcode not supported on this processor: mips1 (mips1) `sdc1 $f8,(8+((4+2)))*4($29)'
> > > | asmpart.S:306: Error: opcode not supported on this processor: mips1 (mips1) `sdc1 $f10,(10+((4+2)))*4($29)'
> > > | asmpart.S:306: Error: opcode not supported on this processor: mips1 (mips1) `sdc1 $f16,(12+((4+2)))*4($29)'
> > > | asmpart.S:306: Error: opcode not supported on this processor: mips1 (mips1) `sdc1 $f18,(14+((4+2)))*4($29)'
> > > | asmpart.S:336: Warning: No .cprestore pseudo-op used in PIC code
> > > | asmpart.S:358: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f12,(4+(0))*4($29)'
> > > | asmpart.S:358: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f14,(6+(0))*4($29)'
> > > | asmpart.S:359: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f8,(8+((4+2)))*4($29)'
> > > | asmpart.S:359: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f10,(10+((4+2)))*4($29)'
> > > | asmpart.S:359: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f16,(12+((4+2)))*4($29)'
> > > | asmpart.S:359: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f18,(14+((4+2)))*4($29)'
> > > | asmpart.S:430: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f20,-4*8($9)'
> > > | asmpart.S:431: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f22,-3*8($9)'
> > > | asmpart.S:432: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f24,-2*8($9)'
> > > | asmpart.S:433: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f26,-1*8($9)'
> > > | asmpart.S:434: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f28,-1*8($9)'
> > > | asmpart.S:435: Error: opcode not supported on this processor: mips1 (mips1) `ldc1 $f30,-1*8($9)'
> > > | asmpart.S:460: Warning: No .cprestore pseudo-op used in PIC code
> > > | asmpart.S:475: Error: opcode not supported on this processor: mips1 (mips1) `ll $2,0($4)'
> > > | asmpart.S:478: Error: opcode not supported on this processor: mips1 (mips1) `sc $8,0($4)'
> > > | asmpart.S:481: Error: opcode not supported on this processor: mips1 (mips1) `sync'
> > > | make[7]: *** [asmpart.lo] Error 1
> > > | make[7]: Leaving directory `/build/buildd/cacao-0.99~rc3/src/vm/jit/mips'
> > > | make[6]: *** [all-recursive] Error 1
> > > | make[6]: Leaving directory `/build/buildd/cacao-0.99~rc3/src/vm/jit/mips'
> > > | make[5]: *** [all-recursive] Error 1
> > > | make[5]: Leaving directory `/build/buildd/cacao-0.99~rc3/src/vm/jit'
> > > | make[4]: *** [all-recursive] Error 1
> > > | make[4]: Leaving directory `/build/buildd/cacao-0.99~rc3/src/vm'
> > > | make[3]: *** [all-recursive] Error 1
> > > | make[3]: Leaving directory `/build/buildd/cacao-0.99~rc3/src'
> > > | make[2]: *** [all-recursive] Error 1
> > > | make[2]: Leaving directory `/build/buildd/cacao-0.99~rc3'
> > > | make[1]: *** [all] Error 2
> > > | make[1]: Leaving directory `/build/buildd/cacao-0.99~rc3'
> > > | make: *** [debian/stamp-makefile-build] Error 2
> > > | dpkg-buildpackage: failure: debian/rules build gave error exit status 2
> > > | ******************************************************************************
> > > | Build finished at 20080505-0258
> > > | FAILED [dpkg-buildpackage died]
> > >
> > > Full build log(s): http://experimental.ftbfs.de/build.php?&ver=0.99~rc3-1&pkg=cacao&arch=mips
> >
> > Upstream told me that this code needs CFLAGS=-mips2. Is this allowed on
> > mips? Are we expected to support mips1 machines?
>
> I honestly have no idea. Redirecting the question to the mips list.
Yes, we should support MIPS I. This isn't too hard, since the Linux
kernel emulates atomic instructions when running on MIPS I (but it
doesn't emulate 64-bit FPU accesses). Those 64-bit FPU instructions are
not supported by the normal O32 ABI which we use in Debian, they should
be replaced by assembler macros which expand to the right instruction
sequence depending on the ABI in effect.
A while ago I provided a patch (in #449185) which tweaks the assembler
code to this effect, and also changes some other bits of code to make
cocoa work on mips/mipsel, however, it appears that only a small part
of it was included in the package.
Appended is an updated version which at least builds for me.
Thiemo
diff -urpN cacao-0.99~rc3.original/src/mm/boehm-gc/include/private/gcconfig.h cacao-0.99~rc3/src/mm/boehm-gc/include/private/gcconfig.h
--- cacao-0.99~rc3.original/src/mm/boehm-gc/include/private/gcconfig.h 2008-02-08 09:17:57.000000000 +0000
+++ cacao-0.99~rc3/src/mm/boehm-gc/include/private/gcconfig.h 2008-05-05 14:48:07.000000000 +0100
@@ -1369,8 +1369,7 @@
# define DYNAMIC_LOADING
extern int _end[];
# define DATAEND (_end)
- extern int __data_start[];
-# define DATASTART ((ptr_t)(__data_start))
+# define SEARCH_FOR_DATA_START
# define ALIGNMENT 4
# define USE_GENERIC_PUSH_REGS
# if __GLIBC__ == 2 && __GLIBC_MINOR__ >= 2 || __GLIBC__ > 2
diff -urpN cacao-0.99~rc3.original/src/vm/jit/mips/asmpart.S cacao-0.99~rc3/src/vm/jit/mips/asmpart.S
--- cacao-0.99~rc3.original/src/vm/jit/mips/asmpart.S 2008-02-08 09:17:57.000000000 +0000
+++ cacao-0.99~rc3/src/vm/jit/mips/asmpart.S 2008-05-05 14:46:12.000000000 +0100
@@ -163,8 +163,7 @@ L_asm_vm_call_method_compute_pv:
# endif
# if !defined(ENABLE_SOFT_FLOAT)
- ldc1 fa0,4*8(t0)
- ldc1 fa1,5*8(t0)
+ l.d fa0,4*8(t0)
# endif
#endif /* SIZEOF_VOID_P == 8 */
@@ -427,12 +426,9 @@ ex_int2:
ldc1 fs3,-1*8(t1)
#else /* SIZEOF_VOID_P == 8 */
# if !defined(ENABLE_SOFT_FLOAT)
- ldc1 fs0,-4*8(t1)
- ldc1 fs1,-3*8(t1)
- ldc1 fs2,-2*8(t1)
- ldc1 fs3,-1*8(t1)
- ldc1 fs4,-1*8(t1)
- ldc1 fs5,-1*8(t1)
+ l.d fs0,-4*8(t1)
+ l.d fs2,-2*8(t1)
+ l.d fs4,-1*8(t1)
# endif /* !defined(ENABLE_SOFT_FLOAT) */
#endif /* SIZEOF_VOID_P == 8 */
@@ -472,13 +468,19 @@ asm_abstractmethoderror:
compare_and_swap:
1:
+ .set mips2
all v0,0(a0)
+ .set mips0
bne v0,a1,2f
move t0,a2
+ .set mips2
asc t0,0(a0)
+ .set mips0
beqz t0,1b
2:
+ .set mips2
sync
+ .set mips0
j ra
.end compare_and_swap
diff -urpN cacao-0.99~rc3.original/src/vm/jit/mips/md-asm.h cacao-0.99~rc3/src/vm/jit/mips/md-asm.h
--- cacao-0.99~rc3.original/src/vm/jit/mips/md-asm.h 2008-02-08 09:17:57.000000000 +0000
+++ cacao-0.99~rc3/src/vm/jit/mips/md-asm.h 2008-05-05 14:56:06.000000000 +0100
@@ -334,12 +334,12 @@
#define SAVE_RETURN_REGISTERS(off) \
sw v0,(0+(off))*4(sp) ; \
sw v1,(1+(off))*4(sp) ; \
- sdc1 fv0,(2+(off))*4(sp) ;
+ s.d fv0,(2+(off))*4(sp) ;
#define RESTORE_RETURN_REGISTERS(off) \
lw v0,(0+(off))*4(sp) ; \
lw v1,(1+(off))*4(sp) ; \
- ldc1 fv0,(2+(off))*4(sp) ;
+ l.d fv0,(2+(off))*4(sp) ;
#define SAVE_ARGUMENT_REGISTERS(off) \
@@ -347,16 +347,14 @@
sw a1,(1+(off))*4(sp) ; \
sw a2,(2+(off))*4(sp) ; \
sw a3,(3+(off))*4(sp) ; \
- sdc1 fa0,(4+(off))*4(sp) ; \
- sdc1 fa1,(6+(off))*4(sp) ;
+ s.d fa0,(4+(off))*4(sp) ;
#define RESTORE_ARGUMENT_REGISTERS(off) \
lw a0,(0+(off))*4(sp) ; \
lw a1,(1+(off))*4(sp) ; \
lw a2,(2+(off))*4(sp) ; \
lw a3,(3+(off))*4(sp) ; \
- ldc1 fa0,(4+(off))*4(sp) ; \
- ldc1 fa1,(6+(off))*4(sp) ;
+ l.d fa0,(4+(off))*4(sp) ;
#define SAVE_TEMPORARY_REGISTERS(off) \
@@ -368,10 +366,8 @@
sw t5,(5+(off))*4(sp) ; \
sw t6,(6+(off))*4(sp) ; \
sw t7,(7+(off))*4(sp) ; \
- sdc1 ft0,(8+(off))*4(sp) ; \
- sdc1 ft1,(10+(off))*4(sp) ; \
- sdc1 ft2,(12+(off))*4(sp) ; \
- sdc1 ft3,(14+(off))*4(sp) ;
+ s.d ft0,(8+(off))*4(sp) ; \
+ s.d ft2,(12+(off))*4(sp) ;
#define RESTORE_TEMPORARY_REGISTERS(off) \
lw t0,(0+(off))*4(sp) ; \
@@ -382,10 +378,8 @@
lw t5,(5+(off))*4(sp) ; \
lw t6,(6+(off))*4(sp) ; \
lw t7,(7+(off))*4(sp) ; \
- ldc1 ft0,(8+(off))*4(sp) ; \
- ldc1 ft1,(10+(off))*4(sp) ; \
- ldc1 ft2,(12+(off))*4(sp) ; \
- ldc1 ft3,(14+(off))*4(sp) ;
+ l.d ft0,(8+(off))*4(sp) ; \
+ l.d ft2,(12+(off))*4(sp) ;
#endif /* SIZEOF_VOID_P == 8 */
--- cacao-0.99~rc3.original/src/vm/jit/mips/linux/md-os.c 2008-04-28 20:52:41.000000000 +0100
+++ cacao-0.99~rc3/src/vm/jit/mips/linux/md-os.c 2008-05-05 17:06:35.000000000 +0100
@@ -43,6 +43,8 @@
#include "vm/exceptions.h"
#include "vm/signallocal.h"
+#include "vm/jit/executionstate.h"
+
#include "vm/jit/asmpart.h"
#include "vm/jit/stacktrace.h"
#include "vm/jit/trap.h"
@@ -253,6 +255,105 @@ void md_signal_handler_sigusr2(int sig,
}
+/* md_executionstate_read ******************************************************
+
+ Read the given context into an executionstate.
+
+*******************************************************************************/
+
+void md_executionstate_read(executionstate_t *es, void *context)
+{
+ ucontext_t *_uc;
+ mcontext_t *_mc;
+ greg_t *_gregs;
+ s4 i;
+
+ _uc = (ucontext_t *) context;
+ _mc = &_uc->uc_mcontext;
+
+#if defined(__UCLIBC__)
+ _gregs = _mc->gpregs;
+#else
+ _gregs = _mc->gregs;
+#endif
+
+ /* read special registers */
+
+ /* In glibc's ucontext.h the registers are defined as long long,
+ even for MIPS32, so we cast them. This is not the case for
+ uClibc. */
+
+ es->pv = (u1 *) (ptrint) _gregs[REG_PV];
+ es->sp = (u1 *) (ptrint) _gregs[REG_SP];
+ es->ra = (u1 *) (ptrint) _gregs[REG_RA]; /* this is correct for leafs */
+#if !defined(__UCLIBC__)
+ es->pc = (u1 *) (ptrint) _mc->pc;
+#else
+ es->pc = (u1 *) (ptrint) _gregs[CTX_EPC];
+#endif
+
+ /* read integer registers */
+ for (i = 0; i < INT_REG_CNT; i++)
+ es->intregs[i] = _gregs[i];
+
+ /* read float registers */
+ /* Do not use the assignment operator '=', as the type of
+ * the _mc->fpregs[i] can cause invalid conversions. */
+
+ assert(sizeof(_mc->fpregs.fp_r) == sizeof(es->fltregs));
+ system_memcpy(&es->fltregs, &_mc->fpregs.fp_r, sizeof(_mc->fpregs.fp_r));
+}
+
+
+/* md_executionstate_write *****************************************************
+
+ Write the given executionstate back to the context.
+
+*******************************************************************************/
+
+void md_executionstate_write(executionstate_t *es, void *context)
+{
+ ucontext_t *_uc;
+ mcontext_t *_mc;
+ greg_t *_gregs;
+ s4 i;
+
+ _uc = (ucontext_t *) context;
+ _mc = &_uc->uc_mcontext;
+
+#if defined(__UCLIBC__)
+ _gregs = _mc->gpregs;
+#else
+ _gregs = _mc->gregs;
+#endif
+
+ /* write integer registers */
+ for (i = 0; i < INT_REG_CNT; i++)
+ _gregs[i] = es->intregs[i];
+
+ /* write float registers */
+ /* Do not use the assignment operator '=', as the type of
+ * the _mc->fpregs[i] can cause invalid conversions. */
+
+ assert(sizeof(_mc->fpregs.fp_r) == sizeof(es->fltregs));
+ system_memcpy(&_mc->fpregs.fp_r, &es->fltregs, sizeof(_mc->fpregs.fp_r));
+
+ /* In glibc's ucontext.h the registers are defined as long long,
+ even for MIPS32, so we cast them. This is not the case for
+ uClibc. */
+
+ /* write special registers */
+ _gregs[REG_PV] = (ptrint) es->pv;
+ _gregs[REG_SP] = (ptrint) es->sp;
+ _gregs[REG_RA] = (ptrint) es->ra;
+#if !defined(__UCLIBC__)
+ _mc->pc = (ptrint) es->pc;
+#else
+ _gregs[CTX_EPC] = (ptrint) es->pc;
+#endif
+}
+
+
/* md_critical_section_restart *************************************************
Search the critical sections tree for a matching section and set
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