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processor serial number: 0073-0F01-0000-0000-0000-0000<br>
MONITOR/MWAIT (5):<br>
smallest monitor-line size (bytes) = 0x40 (64)<br>
largest monitor-line size (bytes) = 0x40 (64)<br>
enum of Monitor-MWAIT exts supported = true<br>
supports intrs as break-event for MWAIT = true<br>
number of C0 sub C-states using MWAIT = 0x0 (0)<br>
number of C1 sub C-states using MWAIT = 0x0 (0)<br>
number of C2 sub C-states using MWAIT = 0x0 (0)<br>
number of C3 sub C-states using MWAIT = 0x0 (0)<br>
number of C4 sub C-states using MWAIT = 0x0 (0)<br>
number of C5 sub C-states using MWAIT = 0x0 (0)<br>
number of C6 sub C-states using MWAIT = 0x0 (0)<br>
number of C7 sub C-states using MWAIT = 0x0 (0)<br>
Thermal and Power Management Features (6):<br>
digital thermometer = false<br>
Intel Turbo Boost Technology = false<br>
ARAT always running APIC timer = false<br>
PLN power limit notification = false<br>
ECMD extended clock modulation duty = false<br>
PTM package thermal management = false<br>
digital thermometer thresholds = 0x0 (0)<br>
ACNT/MCNT supported performance measure = true<br>
ACNT2 available = false<br>
performance-energy bias capability = false<br>
extended feature flags (7):<br>
FSGSBASE instructions = false<br>
IA32_TSC_ADJUST MSR supported = false<br>
BMI instruction = true<br>
HLE hardware lock elision = false<br>
AVX2: advanced vector extensions 2 = false<br>
SMEP supervisor mode exec protection = false<br>
BMI2 instructions = false<br>
enhanced REP MOVSB/STOSB = false<br>
INVPCID instruction = false<br>
RTM: restricted transactional memory = false<br>
QM: quality of service monitoring = false<br>
deprecated FPU CS/DS = false<br>
intel memory protection extensions = false<br>
AVX512F: AVX-512 foundation instructions = false<br>
RDSEED instruction = false<br>
ADX instructions = false<br>
SMAP: supervisor mode access prevention = false<br>
Intel processor trace = false<br>
AVX512PF: prefetch instructions = false<br>
AVX512ER: exponent & reciprocal instrs = false<br>
AVX512CD: conflict detection instrs = false<br>
SHA instructions = false<br>
PREFETCHWT1 = false<br>
Direct Cache Access Parameters (9):<br>
PLATFORM_DCA_CAP MSR bits = 0<br>
Architecture Performance Monitoring Features (0xa/eax):<br>
version ID = 0x0 (0)<br>
number of counters per logical processor = 0x0 (0)<br>
bit width of counter = 0x0 (0)<br>
length of EBX bit vector = 0x0 (0)<br>
Architecture Performance Monitoring Features (0xa/ebx):<br>
core cycle event not available = false<br>
instruction retired event not available = false<br>
reference cycles event not available = false<br>
last-level cache ref event not available = false<br>
last-level cache miss event not avail = false<br>
branch inst retired event not available = false<br>
branch mispred retired event not avail = false<br>
Architecture Performance Monitoring Features (0xa/edx):<br>
number of fixed counters = 0x0 (0)<br>
bit width of fixed counters = 0x0 (0)<br>
XSAVE features (0xd/0):<br>
XCR0 lower 32 bits valid bit field mask = 0x00000007<br>
bytes required by fields in XCR0 = 0x00000340 (832)<br>
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)<br>
XCR0 upper 32 bits valid bit field mask = 0x00000000<br>
YMM features (0xd/2):<br>
YMM save state byte size = 0x00000100 (256)<br>
YMM save state byte offset = 0x00000240 (576)<br>
LWP features (0xd/0x3e):<br>
LWP save state byte size = 0x00000000 (0)<br>
LWP save state byte offset = 0x00000000 (0)<br>
extended processor signature (0x80000001/eax):<br>
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)<br>
model = 0x0 (0)<br>
stepping id = 0x1 (1)<br>
extended family = 0x7 (7)<br>
extended model = 0x3 (3)<br>
(simple synth) = unknown<br>
extended feature flags (0x80000001/edx):<br>
x87 FPU on chip = true<br>
virtual-8086 mode enhancement = true<br>
debugging extensions = true<br>
page size extensions = true<br>
time stamp counter = true<br>
RDMSR and WRMSR support = true<br>
physical address extensions = true<br>
machine check exception = true<br>
CMPXCHG8B inst. = true<br>
APIC on chip = true<br>
SYSCALL and SYSRET instructions = true<br>
memory type range registers = true<br>
global paging extension = true<br>
machine check architecture = true<br>
conditional move/compare instruction = true<br>
page attribute table = true<br>
page size extension = true<br>
multiprocessing capable = false<br>
no-execute page protection = true<br>
AMD multimedia instruction extensions = true<br>
MMX Technology = true<br>
FXSAVE/FXRSTOR = true<br>
SSE extensions = true<br>
1-GB large page support = true<br>
RDTSCP = true<br>
long mode (AA-64) = true<br>
3DNow! instruction extensions = false<br>
3DNow! instructions = false<br>
extended brand id (0x80000001/ebx):<br>
raw = 0x0 (0)<br>
BrandId = 0x0 (0)<br>
AMD feature flags (0x80000001/ecx):<br>
LAHF/SAHF supported in 64-bit mode = true<br>
CMP Legacy = true<br>
SVM: secure virtual machine = true<br>
extended APIC space = true<br>
AltMovCr8 = true<br>
LZCNT advanced bit manipulation = true<br>
SSE4A support = true<br>
misaligned SSE mode = true<br>
3DNow! PREFETCH/PREFETCHW instructions = true<br>
OS visible workaround = true<br>
instruction based sampling = true<br>
XOP support = false<br>
SKINIT/STGI support = true<br>
watchdog timer support = true<br>
lightweight profiling support = false<br>
4-operand FMA instruction = false<br>
NodeId MSR C001100C = false<br>
TBM support = false<br>
topology extensions = true<br>
brand = "AMD A6-6310 APU with AMD Radeon R4 Graphics "<br>
L1 TLB/cache information: 2M/4M pages & L1 TLB
(0x80000005/eax):<br>
instruction # entries = 0x8 (8)<br>
instruction associativity = 0xff (255)<br>
data # entries = 0x8 (8)<br>
data associativity = 0xff (255)<br>
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):<br>
instruction # entries = 0x20 (32)<br>
instruction associativity = 0xff (255)<br>
data # entries = 0x28 (40)<br>
data associativity = 0xff (255)<br>
L1 data cache information (0x80000005/ecx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 0x8 (8)<br>
size (Kb) = 0x20 (32)<br>
L1 instruction cache information (0x80000005/edx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 0x2 (2)<br>
size (Kb) = 0x20 (32)<br>
L2 TLB/cache information: 2M/4M pages & L2 TLB
(0x80000006/eax):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x100 (256)<br>
data associativity = 2-way (2)<br>
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):<br>
instruction # entries = 0x200 (512)<br>
instruction associativity = 4-way (4)<br>
data # entries = 0x200 (512)<br>
data associativity = 4-way (4)<br>
L2 unified cache information (0x80000006/ecx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 16-way (8)<br>
size (Kb) = 0x800 (2048)<br>
L3 cache information (0x80000006/edx):<br>
line size (bytes) = 0x0 (0)<br>
lines per tag = 0x0 (0)<br>
associativity = L2 off (0)<br>
size (in 512Kb units) = 0x0 (0)<br>
Advanced Power Management Features (0x80000007/edx):<br>
temperature sensing diode = true<br>
frequency ID (FID) control = false<br>
voltage ID (VID) control = false<br>
thermal trip (TTP) = true<br>
thermal monitor (TM) = true<br>
software thermal control (STC) = false<br>
100 MHz multiplier control = true<br>
hardware P-State control = true<br>
TscInvariant = true<br>
Physical Address and Linear Address Size (0x80000008/eax):<br>
maximum physical address bits = 0x28 (40)<br>
maximum linear (virtual) address bits = 0x30 (48)<br>
maximum guest physical address bits = 0x0 (0)<br>
Logical CPU cores (0x80000008/ecx):<br>
number of CPU cores - 1 = 0x3 (3)<br>
ApicIdCoreIdSize = 0x3 (3)<br>
SVM Secure Virtual Machine (0x8000000a/eax):<br>
SvmRev: SVM revision = 0x1 (1)<br>
SVM Secure Virtual Machine (0x8000000a/edx):<br>
nested paging = true<br>
LBR virtualization = true<br>
SVM lock = true<br>
NRIP save = true<br>
MSR based TSC rate control = true<br>
VMCB clean bits support = false<br>
flush by ASID = true<br>
decode assists = true<br>
SSSE3/SSE5 opcode set disable = false<br>
pause intercept filter = true<br>
pause filter threshold = true<br>
NASID: number of address space identifiers = 0x8 (8):<br>
L1 TLB information: 1G pages (0x80000019/eax):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x0 (0)<br>
data associativity = L2 off (0)<br>
L2 TLB information: 1G pages (0x80000019/ebx):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x0 (0)<br>
data associativity = L2 off (0)<br>
SVM Secure Virtual Machine (0x8000001a/eax):<br>
128-bit SSE executed full-width = true<br>
MOVU* better than MOVL*/MOVH* = true<br>
Instruction Based Sampling Identifiers (0x8000001b/eax):<br>
IBS feature flags valid = true<br>
IBS fetch sampling = true<br>
IBS execution sampling = true<br>
read write of op counter = true<br>
op counting mode = true<br>
branch target address reporting = true<br>
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true<br>
invalid RIP indication supported = true<br>
Lightweight Profiling Capabilities: Availability
(0x8000001c/eax):<br>
lightweight profiling = false<br>
LWPVAL instruction = false<br>
instruction retired event = false<br>
branch retired event = false<br>
DC miss event = false<br>
core clocks not halted event = false<br>
core reference clocks not halted event = false<br>
interrupt on threshold overflow = false<br>
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):<br>
lightweight profiling = false<br>
LWPVAL instruction = false<br>
instruction retired event = false<br>
branch retired event = false<br>
DC miss event = false<br>
core clocks not halted event = false<br>
core reference clocks not halted event = false<br>
interrupt on threshold overflow = false<br>
Lightweight Profiling Capabilities (0x8000001c/ebx):<br>
LWPCB byte size = 0x0 (0)<br>
event record byte size = 0x0 (0)<br>
maximum EventId = 0x0 (0)<br>
EventInterval1 field offset = 0x0 (0)<br>
Lightweight Profiling Capabilities (0x8000001c/ecx):<br>
latency counter bit size = 0x0 (0)<br>
data cache miss address valid = false<br>
amount cache latency is rounded = 0x0 (0)<br>
LWP implementation version = 0x0 (0)<br>
event ring buffer size in records = 0x0 (0)<br>
branch prediction filtering = false<br>
IP filtering = false<br>
cache level filtering = false<br>
cache latency filteing = false<br>
--- cache 0 ---<br>
type = data (1)<br>
level = 0x1 (1)<br>
self-initializing = true<br>
fully associative = false<br>
extra cores sharing this cache = 0x0 (0)<br>
line size in bytes = 0x3f (63)<br>
physical line partitions = 0x0 (0)<br>
number of ways = 0x7 (7)<br>
number of sets = 63<br>
write-back invalidate = false<br>
cache inclusive of lower levels = false<br>
extended APIC ID = 1<br>
Extended APIC ID (0x8000001e/ebx):<br>
compute unit ID = 0x1 (1)<br>
cores per compute unit - 1 = 0x0 (0)<br>
Extended APIC ID (0x8000001e/ecx):<br>
node ID = 0x0 (0)<br>
nodes per processor = 1 node (0)<br>
(instruction supported synth):<br>
CMPXCHG8B = true<br>
conditional move/compare = true<br>
PREFETCH/PREFETCHW = true<br>
(multi-processing synth): multi-core (c=4)<br>
(multi-processing method): AMD<br>
(APIC widths synth): CORE_width=2 SMT_width=0<br>
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0<br>
(synth) = unknown<br>
CPU 2:<br>
vendor_id = "AuthenticAMD"<br>
version information (1/eax):<br>
processor type = primary processor (0)<br>
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)<br>
model = 0x0 (0)<br>
stepping id = 0x1 (1)<br>
extended family = 0x7 (7)<br>
extended model = 0x3 (3)<br>
(simple synth) = unknown<br>
miscellaneous (1/ebx):<br>
process local APIC physical ID = 0x2 (2)<br>
cpu count = 0x4 (4)<br>
CLFLUSH line size = 0x8 (8)<br>
brand index = 0x0 (0)<br>
brand id = 0x00 (0): unknown<br>
feature information (1/edx):<br>
x87 FPU on chip = true<br>
virtual-8086 mode enhancement = true<br>
debugging extensions = true<br>
page size extensions = true<br>
time stamp counter = true<br>
RDMSR and WRMSR support = true<br>
physical address extensions = true<br>
machine check exception = true<br>
CMPXCHG8B inst. = true<br>
APIC on chip = true<br>
SYSENTER and SYSEXIT = true<br>
memory type range registers = true<br>
PTE global bit = true<br>
machine check architecture = true<br>
conditional move/compare instruction = true<br>
page attribute table = true<br>
page size extension = true<br>
processor serial number = false<br>
CLFLUSH instruction = true<br>
debug store = false<br>
thermal monitor and clock ctrl = false<br>
MMX Technology = true<br>
FXSAVE/FXRSTOR = true<br>
SSE extensions = true<br>
SSE2 extensions = true<br>
self snoop = false<br>
hyper-threading / multi-core supported = true<br>
therm. monitor = false<br>
IA64 = false<br>
pending break event = false<br>
feature information (1/ecx):<br>
PNI/SSE3: Prescott New Instructions = true<br>
PCLMULDQ instruction = true<br>
64-bit debug store = false<br>
MONITOR/MWAIT = true<br>
CPL-qualified debug store = false<br>
VMX: virtual machine extensions = false<br>
SMX: safer mode extensions = false<br>
Enhanced Intel SpeedStep Technology = false<br>
thermal monitor 2 = false<br>
SSSE3 extensions = true<br>
context ID: adaptive or shared L1 data = false<br>
FMA instruction = false<br>
CMPXCHG16B instruction = true<br>
xTPR disable = false<br>
perfmon and debug = false<br>
process context identifiers = false<br>
direct cache access = false<br>
SSE4.1 extensions = true<br>
SSE4.2 extensions = true<br>
extended xAPIC support = false<br>
MOVBE instruction = true<br>
POPCNT instruction = true<br>
time stamp counter deadline = false<br>
AES instruction = true<br>
XSAVE/XSTOR states = true<br>
OS-enabled XSAVE/XSTOR = true<br>
AVX: advanced vector extensions = true<br>
F16C half-precision convert instruction = true<br>
RDRAND instruction = true<br>
hypervisor guest status = false<br>
cache and TLB information (2):<br>
processor serial number: 0073-0F01-0000-0000-0000-0000<br>
MONITOR/MWAIT (5):<br>
smallest monitor-line size (bytes) = 0x40 (64)<br>
largest monitor-line size (bytes) = 0x40 (64)<br>
enum of Monitor-MWAIT exts supported = true<br>
supports intrs as break-event for MWAIT = true<br>
number of C0 sub C-states using MWAIT = 0x0 (0)<br>
number of C1 sub C-states using MWAIT = 0x0 (0)<br>
number of C2 sub C-states using MWAIT = 0x0 (0)<br>
number of C3 sub C-states using MWAIT = 0x0 (0)<br>
number of C4 sub C-states using MWAIT = 0x0 (0)<br>
number of C5 sub C-states using MWAIT = 0x0 (0)<br>
number of C6 sub C-states using MWAIT = 0x0 (0)<br>
number of C7 sub C-states using MWAIT = 0x0 (0)<br>
Thermal and Power Management Features (6):<br>
digital thermometer = false<br>
Intel Turbo Boost Technology = false<br>
ARAT always running APIC timer = false<br>
PLN power limit notification = false<br>
ECMD extended clock modulation duty = false<br>
PTM package thermal management = false<br>
digital thermometer thresholds = 0x0 (0)<br>
ACNT/MCNT supported performance measure = true<br>
ACNT2 available = false<br>
performance-energy bias capability = false<br>
extended feature flags (7):<br>
FSGSBASE instructions = false<br>
IA32_TSC_ADJUST MSR supported = false<br>
BMI instruction = true<br>
HLE hardware lock elision = false<br>
AVX2: advanced vector extensions 2 = false<br>
SMEP supervisor mode exec protection = false<br>
BMI2 instructions = false<br>
enhanced REP MOVSB/STOSB = false<br>
INVPCID instruction = false<br>
RTM: restricted transactional memory = false<br>
QM: quality of service monitoring = false<br>
deprecated FPU CS/DS = false<br>
intel memory protection extensions = false<br>
AVX512F: AVX-512 foundation instructions = false<br>
RDSEED instruction = false<br>
ADX instructions = false<br>
SMAP: supervisor mode access prevention = false<br>
Intel processor trace = false<br>
AVX512PF: prefetch instructions = false<br>
AVX512ER: exponent & reciprocal instrs = false<br>
AVX512CD: conflict detection instrs = false<br>
SHA instructions = false<br>
PREFETCHWT1 = false<br>
Direct Cache Access Parameters (9):<br>
PLATFORM_DCA_CAP MSR bits = 0<br>
Architecture Performance Monitoring Features (0xa/eax):<br>
version ID = 0x0 (0)<br>
number of counters per logical processor = 0x0 (0)<br>
bit width of counter = 0x0 (0)<br>
length of EBX bit vector = 0x0 (0)<br>
Architecture Performance Monitoring Features (0xa/ebx):<br>
core cycle event not available = false<br>
instruction retired event not available = false<br>
reference cycles event not available = false<br>
last-level cache ref event not available = false<br>
last-level cache miss event not avail = false<br>
branch inst retired event not available = false<br>
branch mispred retired event not avail = false<br>
Architecture Performance Monitoring Features (0xa/edx):<br>
number of fixed counters = 0x0 (0)<br>
bit width of fixed counters = 0x0 (0)<br>
XSAVE features (0xd/0):<br>
XCR0 lower 32 bits valid bit field mask = 0x00000007<br>
bytes required by fields in XCR0 = 0x00000340 (832)<br>
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)<br>
XCR0 upper 32 bits valid bit field mask = 0x00000000<br>
YMM features (0xd/2):<br>
YMM save state byte size = 0x00000100 (256)<br>
YMM save state byte offset = 0x00000240 (576)<br>
LWP features (0xd/0x3e):<br>
LWP save state byte size = 0x00000000 (0)<br>
LWP save state byte offset = 0x00000000 (0)<br>
extended processor signature (0x80000001/eax):<br>
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)<br>
model = 0x0 (0)<br>
stepping id = 0x1 (1)<br>
extended family = 0x7 (7)<br>
extended model = 0x3 (3)<br>
(simple synth) = unknown<br>
extended feature flags (0x80000001/edx):<br>
x87 FPU on chip = true<br>
virtual-8086 mode enhancement = true<br>
debugging extensions = true<br>
page size extensions = true<br>
time stamp counter = true<br>
RDMSR and WRMSR support = true<br>
physical address extensions = true<br>
machine check exception = true<br>
CMPXCHG8B inst. = true<br>
APIC on chip = true<br>
SYSCALL and SYSRET instructions = true<br>
memory type range registers = true<br>
global paging extension = true<br>
machine check architecture = true<br>
conditional move/compare instruction = true<br>
page attribute table = true<br>
page size extension = true<br>
multiprocessing capable = false<br>
no-execute page protection = true<br>
AMD multimedia instruction extensions = true<br>
MMX Technology = true<br>
FXSAVE/FXRSTOR = true<br>
SSE extensions = true<br>
1-GB large page support = true<br>
RDTSCP = true<br>
long mode (AA-64) = true<br>
3DNow! instruction extensions = false<br>
3DNow! instructions = false<br>
extended brand id (0x80000001/ebx):<br>
raw = 0x0 (0)<br>
BrandId = 0x0 (0)<br>
AMD feature flags (0x80000001/ecx):<br>
LAHF/SAHF supported in 64-bit mode = true<br>
CMP Legacy = true<br>
SVM: secure virtual machine = true<br>
extended APIC space = true<br>
AltMovCr8 = true<br>
LZCNT advanced bit manipulation = true<br>
SSE4A support = true<br>
misaligned SSE mode = true<br>
3DNow! PREFETCH/PREFETCHW instructions = true<br>
OS visible workaround = true<br>
instruction based sampling = true<br>
XOP support = false<br>
SKINIT/STGI support = true<br>
watchdog timer support = true<br>
lightweight profiling support = false<br>
4-operand FMA instruction = false<br>
NodeId MSR C001100C = false<br>
TBM support = false<br>
topology extensions = true<br>
brand = "AMD A6-6310 APU with AMD Radeon R4 Graphics "<br>
L1 TLB/cache information: 2M/4M pages & L1 TLB
(0x80000005/eax):<br>
instruction # entries = 0x8 (8)<br>
instruction associativity = 0xff (255)<br>
data # entries = 0x8 (8)<br>
data associativity = 0xff (255)<br>
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):<br>
instruction # entries = 0x20 (32)<br>
instruction associativity = 0xff (255)<br>
data # entries = 0x28 (40)<br>
data associativity = 0xff (255)<br>
L1 data cache information (0x80000005/ecx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 0x8 (8)<br>
size (Kb) = 0x20 (32)<br>
L1 instruction cache information (0x80000005/edx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 0x2 (2)<br>
size (Kb) = 0x20 (32)<br>
L2 TLB/cache information: 2M/4M pages & L2 TLB
(0x80000006/eax):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x100 (256)<br>
data associativity = 2-way (2)<br>
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):<br>
instruction # entries = 0x200 (512)<br>
instruction associativity = 4-way (4)<br>
data # entries = 0x200 (512)<br>
data associativity = 4-way (4)<br>
L2 unified cache information (0x80000006/ecx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 16-way (8)<br>
size (Kb) = 0x800 (2048)<br>
L3 cache information (0x80000006/edx):<br>
line size (bytes) = 0x0 (0)<br>
lines per tag = 0x0 (0)<br>
associativity = L2 off (0)<br>
size (in 512Kb units) = 0x0 (0)<br>
Advanced Power Management Features (0x80000007/edx):<br>
temperature sensing diode = true<br>
frequency ID (FID) control = false<br>
voltage ID (VID) control = false<br>
thermal trip (TTP) = true<br>
thermal monitor (TM) = true<br>
software thermal control (STC) = false<br>
100 MHz multiplier control = true<br>
hardware P-State control = true<br>
TscInvariant = true<br>
Physical Address and Linear Address Size (0x80000008/eax):<br>
maximum physical address bits = 0x28 (40)<br>
maximum linear (virtual) address bits = 0x30 (48)<br>
maximum guest physical address bits = 0x0 (0)<br>
Logical CPU cores (0x80000008/ecx):<br>
number of CPU cores - 1 = 0x3 (3)<br>
ApicIdCoreIdSize = 0x3 (3)<br>
SVM Secure Virtual Machine (0x8000000a/eax):<br>
SvmRev: SVM revision = 0x1 (1)<br>
SVM Secure Virtual Machine (0x8000000a/edx):<br>
nested paging = true<br>
LBR virtualization = true<br>
SVM lock = true<br>
NRIP save = true<br>
MSR based TSC rate control = true<br>
VMCB clean bits support = false<br>
flush by ASID = true<br>
decode assists = true<br>
SSSE3/SSE5 opcode set disable = false<br>
pause intercept filter = true<br>
pause filter threshold = true<br>
NASID: number of address space identifiers = 0x8 (8):<br>
L1 TLB information: 1G pages (0x80000019/eax):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x0 (0)<br>
data associativity = L2 off (0)<br>
L2 TLB information: 1G pages (0x80000019/ebx):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x0 (0)<br>
data associativity = L2 off (0)<br>
SVM Secure Virtual Machine (0x8000001a/eax):<br>
128-bit SSE executed full-width = true<br>
MOVU* better than MOVL*/MOVH* = true<br>
Instruction Based Sampling Identifiers (0x8000001b/eax):<br>
IBS feature flags valid = true<br>
IBS fetch sampling = true<br>
IBS execution sampling = true<br>
read write of op counter = true<br>
op counting mode = true<br>
branch target address reporting = true<br>
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true<br>
invalid RIP indication supported = true<br>
Lightweight Profiling Capabilities: Availability
(0x8000001c/eax):<br>
lightweight profiling = false<br>
LWPVAL instruction = false<br>
instruction retired event = false<br>
branch retired event = false<br>
DC miss event = false<br>
core clocks not halted event = false<br>
core reference clocks not halted event = false<br>
interrupt on threshold overflow = false<br>
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):<br>
lightweight profiling = false<br>
LWPVAL instruction = false<br>
instruction retired event = false<br>
branch retired event = false<br>
DC miss event = false<br>
core clocks not halted event = false<br>
core reference clocks not halted event = false<br>
interrupt on threshold overflow = false<br>
Lightweight Profiling Capabilities (0x8000001c/ebx):<br>
LWPCB byte size = 0x0 (0)<br>
event record byte size = 0x0 (0)<br>
maximum EventId = 0x0 (0)<br>
EventInterval1 field offset = 0x0 (0)<br>
Lightweight Profiling Capabilities (0x8000001c/ecx):<br>
latency counter bit size = 0x0 (0)<br>
data cache miss address valid = false<br>
amount cache latency is rounded = 0x0 (0)<br>
LWP implementation version = 0x0 (0)<br>
event ring buffer size in records = 0x0 (0)<br>
branch prediction filtering = false<br>
IP filtering = false<br>
cache level filtering = false<br>
cache latency filteing = false<br>
--- cache 0 ---<br>
type = data (1)<br>
level = 0x1 (1)<br>
self-initializing = true<br>
fully associative = false<br>
extra cores sharing this cache = 0x0 (0)<br>
line size in bytes = 0x3f (63)<br>
physical line partitions = 0x0 (0)<br>
number of ways = 0x7 (7)<br>
number of sets = 63<br>
write-back invalidate = false<br>
cache inclusive of lower levels = false<br>
extended APIC ID = 2<br>
Extended APIC ID (0x8000001e/ebx):<br>
compute unit ID = 0x2 (2)<br>
cores per compute unit - 1 = 0x0 (0)<br>
Extended APIC ID (0x8000001e/ecx):<br>
node ID = 0x0 (0)<br>
nodes per processor = 1 node (0)<br>
(instruction supported synth):<br>
CMPXCHG8B = true<br>
conditional move/compare = true<br>
PREFETCH/PREFETCHW = true<br>
(multi-processing synth): multi-core (c=4)<br>
(multi-processing method): AMD<br>
(APIC widths synth): CORE_width=2 SMT_width=0<br>
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0<br>
(synth) = unknown<br>
CPU 3:<br>
vendor_id = "AuthenticAMD"<br>
version information (1/eax):<br>
processor type = primary processor (0)<br>
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)<br>
model = 0x0 (0)<br>
stepping id = 0x1 (1)<br>
extended family = 0x7 (7)<br>
extended model = 0x3 (3)<br>
(simple synth) = unknown<br>
miscellaneous (1/ebx):<br>
process local APIC physical ID = 0x3 (3)<br>
cpu count = 0x4 (4)<br>
CLFLUSH line size = 0x8 (8)<br>
brand index = 0x0 (0)<br>
brand id = 0x00 (0): unknown<br>
feature information (1/edx):<br>
x87 FPU on chip = true<br>
virtual-8086 mode enhancement = true<br>
debugging extensions = true<br>
page size extensions = true<br>
time stamp counter = true<br>
RDMSR and WRMSR support = true<br>
physical address extensions = true<br>
machine check exception = true<br>
CMPXCHG8B inst. = true<br>
APIC on chip = true<br>
SYSENTER and SYSEXIT = true<br>
memory type range registers = true<br>
PTE global bit = true<br>
machine check architecture = true<br>
conditional move/compare instruction = true<br>
page attribute table = true<br>
page size extension = true<br>
processor serial number = false<br>
CLFLUSH instruction = true<br>
debug store = false<br>
thermal monitor and clock ctrl = false<br>
MMX Technology = true<br>
FXSAVE/FXRSTOR = true<br>
SSE extensions = true<br>
SSE2 extensions = true<br>
self snoop = false<br>
hyper-threading / multi-core supported = true<br>
therm. monitor = false<br>
IA64 = false<br>
pending break event = false<br>
feature information (1/ecx):<br>
PNI/SSE3: Prescott New Instructions = true<br>
PCLMULDQ instruction = true<br>
64-bit debug store = false<br>
MONITOR/MWAIT = true<br>
CPL-qualified debug store = false<br>
VMX: virtual machine extensions = false<br>
SMX: safer mode extensions = false<br>
Enhanced Intel SpeedStep Technology = false<br>
thermal monitor 2 = false<br>
SSSE3 extensions = true<br>
context ID: adaptive or shared L1 data = false<br>
FMA instruction = false<br>
CMPXCHG16B instruction = true<br>
xTPR disable = false<br>
perfmon and debug = false<br>
process context identifiers = false<br>
direct cache access = false<br>
SSE4.1 extensions = true<br>
SSE4.2 extensions = true<br>
extended xAPIC support = false<br>
MOVBE instruction = true<br>
POPCNT instruction = true<br>
time stamp counter deadline = false<br>
AES instruction = true<br>
XSAVE/XSTOR states = true<br>
OS-enabled XSAVE/XSTOR = true<br>
AVX: advanced vector extensions = true<br>
F16C half-precision convert instruction = true<br>
RDRAND instruction = true<br>
hypervisor guest status = false<br>
cache and TLB information (2):<br>
processor serial number: 0073-0F01-0000-0000-0000-0000<br>
MONITOR/MWAIT (5):<br>
smallest monitor-line size (bytes) = 0x40 (64)<br>
largest monitor-line size (bytes) = 0x40 (64)<br>
enum of Monitor-MWAIT exts supported = true<br>
supports intrs as break-event for MWAIT = true<br>
number of C0 sub C-states using MWAIT = 0x0 (0)<br>
number of C1 sub C-states using MWAIT = 0x0 (0)<br>
number of C2 sub C-states using MWAIT = 0x0 (0)<br>
number of C3 sub C-states using MWAIT = 0x0 (0)<br>
number of C4 sub C-states using MWAIT = 0x0 (0)<br>
number of C5 sub C-states using MWAIT = 0x0 (0)<br>
number of C6 sub C-states using MWAIT = 0x0 (0)<br>
number of C7 sub C-states using MWAIT = 0x0 (0)<br>
Thermal and Power Management Features (6):<br>
digital thermometer = false<br>
Intel Turbo Boost Technology = false<br>
ARAT always running APIC timer = false<br>
PLN power limit notification = false<br>
ECMD extended clock modulation duty = false<br>
PTM package thermal management = false<br>
digital thermometer thresholds = 0x0 (0)<br>
ACNT/MCNT supported performance measure = true<br>
ACNT2 available = false<br>
performance-energy bias capability = false<br>
extended feature flags (7):<br>
FSGSBASE instructions = false<br>
IA32_TSC_ADJUST MSR supported = false<br>
BMI instruction = true<br>
HLE hardware lock elision = false<br>
AVX2: advanced vector extensions 2 = false<br>
SMEP supervisor mode exec protection = false<br>
BMI2 instructions = false<br>
enhanced REP MOVSB/STOSB = false<br>
INVPCID instruction = false<br>
RTM: restricted transactional memory = false<br>
QM: quality of service monitoring = false<br>
deprecated FPU CS/DS = false<br>
intel memory protection extensions = false<br>
AVX512F: AVX-512 foundation instructions = false<br>
RDSEED instruction = false<br>
ADX instructions = false<br>
SMAP: supervisor mode access prevention = false<br>
Intel processor trace = false<br>
AVX512PF: prefetch instructions = false<br>
AVX512ER: exponent & reciprocal instrs = false<br>
AVX512CD: conflict detection instrs = false<br>
SHA instructions = false<br>
PREFETCHWT1 = false<br>
Direct Cache Access Parameters (9):<br>
PLATFORM_DCA_CAP MSR bits = 0<br>
Architecture Performance Monitoring Features (0xa/eax):<br>
version ID = 0x0 (0)<br>
number of counters per logical processor = 0x0 (0)<br>
bit width of counter = 0x0 (0)<br>
length of EBX bit vector = 0x0 (0)<br>
Architecture Performance Monitoring Features (0xa/ebx):<br>
core cycle event not available = false<br>
instruction retired event not available = false<br>
reference cycles event not available = false<br>
last-level cache ref event not available = false<br>
last-level cache miss event not avail = false<br>
branch inst retired event not available = false<br>
branch mispred retired event not avail = false<br>
Architecture Performance Monitoring Features (0xa/edx):<br>
number of fixed counters = 0x0 (0)<br>
bit width of fixed counters = 0x0 (0)<br>
XSAVE features (0xd/0):<br>
XCR0 lower 32 bits valid bit field mask = 0x00000007<br>
bytes required by fields in XCR0 = 0x00000340 (832)<br>
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)<br>
XCR0 upper 32 bits valid bit field mask = 0x00000000<br>
YMM features (0xd/2):<br>
YMM save state byte size = 0x00000100 (256)<br>
YMM save state byte offset = 0x00000240 (576)<br>
LWP features (0xd/0x3e):<br>
LWP save state byte size = 0x00000000 (0)<br>
LWP save state byte offset = 0x00000000 (0)<br>
extended processor signature (0x80000001/eax):<br>
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)<br>
model = 0x0 (0)<br>
stepping id = 0x1 (1)<br>
extended family = 0x7 (7)<br>
extended model = 0x3 (3)<br>
(simple synth) = unknown<br>
extended feature flags (0x80000001/edx):<br>
x87 FPU on chip = true<br>
virtual-8086 mode enhancement = true<br>
debugging extensions = true<br>
page size extensions = true<br>
time stamp counter = true<br>
RDMSR and WRMSR support = true<br>
physical address extensions = true<br>
machine check exception = true<br>
CMPXCHG8B inst. = true<br>
APIC on chip = true<br>
SYSCALL and SYSRET instructions = true<br>
memory type range registers = true<br>
global paging extension = true<br>
machine check architecture = true<br>
conditional move/compare instruction = true<br>
page attribute table = true<br>
page size extension = true<br>
multiprocessing capable = false<br>
no-execute page protection = true<br>
AMD multimedia instruction extensions = true<br>
MMX Technology = true<br>
FXSAVE/FXRSTOR = true<br>
SSE extensions = true<br>
1-GB large page support = true<br>
RDTSCP = true<br>
long mode (AA-64) = true<br>
3DNow! instruction extensions = false<br>
3DNow! instructions = false<br>
extended brand id (0x80000001/ebx):<br>
raw = 0x0 (0)<br>
BrandId = 0x0 (0)<br>
AMD feature flags (0x80000001/ecx):<br>
LAHF/SAHF supported in 64-bit mode = true<br>
CMP Legacy = true<br>
SVM: secure virtual machine = true<br>
extended APIC space = true<br>
AltMovCr8 = true<br>
LZCNT advanced bit manipulation = true<br>
SSE4A support = true<br>
misaligned SSE mode = true<br>
3DNow! PREFETCH/PREFETCHW instructions = true<br>
OS visible workaround = true<br>
instruction based sampling = true<br>
XOP support = false<br>
SKINIT/STGI support = true<br>
watchdog timer support = true<br>
lightweight profiling support = false<br>
4-operand FMA instruction = false<br>
NodeId MSR C001100C = false<br>
TBM support = false<br>
topology extensions = true<br>
brand = "AMD A6-6310 APU with AMD Radeon R4 Graphics "<br>
L1 TLB/cache information: 2M/4M pages & L1 TLB
(0x80000005/eax):<br>
instruction # entries = 0x8 (8)<br>
instruction associativity = 0xff (255)<br>
data # entries = 0x8 (8)<br>
data associativity = 0xff (255)<br>
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):<br>
instruction # entries = 0x20 (32)<br>
instruction associativity = 0xff (255)<br>
data # entries = 0x28 (40)<br>
data associativity = 0xff (255)<br>
L1 data cache information (0x80000005/ecx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 0x8 (8)<br>
size (Kb) = 0x20 (32)<br>
L1 instruction cache information (0x80000005/edx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 0x2 (2)<br>
size (Kb) = 0x20 (32)<br>
L2 TLB/cache information: 2M/4M pages & L2 TLB
(0x80000006/eax):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x100 (256)<br>
data associativity = 2-way (2)<br>
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):<br>
instruction # entries = 0x200 (512)<br>
instruction associativity = 4-way (4)<br>
data # entries = 0x200 (512)<br>
data associativity = 4-way (4)<br>
L2 unified cache information (0x80000006/ecx):<br>
line size (bytes) = 0x40 (64)<br>
lines per tag = 0x1 (1)<br>
associativity = 16-way (8)<br>
size (Kb) = 0x800 (2048)<br>
L3 cache information (0x80000006/edx):<br>
line size (bytes) = 0x0 (0)<br>
lines per tag = 0x0 (0)<br>
associativity = L2 off (0)<br>
size (in 512Kb units) = 0x0 (0)<br>
Advanced Power Management Features (0x80000007/edx):<br>
temperature sensing diode = true<br>
frequency ID (FID) control = false<br>
voltage ID (VID) control = false<br>
thermal trip (TTP) = true<br>
thermal monitor (TM) = true<br>
software thermal control (STC) = false<br>
100 MHz multiplier control = true<br>
hardware P-State control = true<br>
TscInvariant = true<br>
Physical Address and Linear Address Size (0x80000008/eax):<br>
maximum physical address bits = 0x28 (40)<br>
maximum linear (virtual) address bits = 0x30 (48)<br>
maximum guest physical address bits = 0x0 (0)<br>
Logical CPU cores (0x80000008/ecx):<br>
number of CPU cores - 1 = 0x3 (3)<br>
ApicIdCoreIdSize = 0x3 (3)<br>
SVM Secure Virtual Machine (0x8000000a/eax):<br>
SvmRev: SVM revision = 0x1 (1)<br>
SVM Secure Virtual Machine (0x8000000a/edx):<br>
nested paging = true<br>
LBR virtualization = true<br>
SVM lock = true<br>
NRIP save = true<br>
MSR based TSC rate control = true<br>
VMCB clean bits support = false<br>
flush by ASID = true<br>
decode assists = true<br>
SSSE3/SSE5 opcode set disable = false<br>
pause intercept filter = true<br>
pause filter threshold = true<br>
NASID: number of address space identifiers = 0x8 (8):<br>
L1 TLB information: 1G pages (0x80000019/eax):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x0 (0)<br>
data associativity = L2 off (0)<br>
L2 TLB information: 1G pages (0x80000019/ebx):<br>
instruction # entries = 0x0 (0)<br>
instruction associativity = L2 off (0)<br>
data # entries = 0x0 (0)<br>
data associativity = L2 off (0)<br>
SVM Secure Virtual Machine (0x8000001a/eax):<br>
128-bit SSE executed full-width = true<br>
MOVU* better than MOVL*/MOVH* = true<br>
Instruction Based Sampling Identifiers (0x8000001b/eax):<br>
IBS feature flags valid = true<br>
IBS fetch sampling = true<br>
IBS execution sampling = true<br>
read write of op counter = true<br>
op counting mode = true<br>
branch target address reporting = true<br>
IbsOpCurCnt and IbsOpMaxCnt extend 7 = true<br>
invalid RIP indication supported = true<br>
Lightweight Profiling Capabilities: Availability
(0x8000001c/eax):<br>
lightweight profiling = false<br>
LWPVAL instruction = false<br>
instruction retired event = false<br>
branch retired event = false<br>
DC miss event = false<br>
core clocks not halted event = false<br>
core reference clocks not halted event = false<br>
interrupt on threshold overflow = false<br>
Lightweight Profiling Capabilities: Supported (0x8000001c/edx):<br>
lightweight profiling = false<br>
LWPVAL instruction = false<br>
instruction retired event = false<br>
branch retired event = false<br>
DC miss event = false<br>
core clocks not halted event = false<br>
core reference clocks not halted event = false<br>
interrupt on threshold overflow = false<br>
Lightweight Profiling Capabilities (0x8000001c/ebx):<br>
LWPCB byte size = 0x0 (0)<br>
event record byte size = 0x0 (0)<br>
maximum EventId = 0x0 (0)<br>
EventInterval1 field offset = 0x0 (0)<br>
Lightweight Profiling Capabilities (0x8000001c/ecx):<br>
latency counter bit size = 0x0 (0)<br>
data cache miss address valid = false<br>
amount cache latency is rounded = 0x0 (0)<br>
LWP implementation version = 0x0 (0)<br>
event ring buffer size in records = 0x0 (0)<br>
branch prediction filtering = false<br>
IP filtering = false<br>
cache level filtering = false<br>
cache latency filteing = false<br>
--- cache 0 ---<br>
type = data (1)<br>
level = 0x1 (1)<br>
self-initializing = true<br>
fully associative = false<br>
extra cores sharing this cache = 0x0 (0)<br>
line size in bytes = 0x3f (63)<br>
physical line partitions = 0x0 (0)<br>
number of ways = 0x7 (7)<br>
number of sets = 63<br>
write-back invalidate = false<br>
cache inclusive of lower levels = false<br>
extended APIC ID = 3<br>
Extended APIC ID (0x8000001e/ebx):<br>
compute unit ID = 0x3 (3)<br>
cores per compute unit - 1 = 0x0 (0)<br>
Extended APIC ID (0x8000001e/ecx):<br>
node ID = 0x0 (0)<br>
nodes per processor = 1 node (0)<br>
(instruction supported synth):<br>
CMPXCHG8B = true<br>
conditional move/compare = true<br>
PREFETCH/PREFETCHW = true<br>
(multi-processing synth): multi-core (c=4)<br>
(multi-processing method): AMD<br>
(APIC widths synth): CORE_width=2 SMT_width=0<br>
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0<br>
(synth) = unknown<br>
root@notosh:/home/ckosloff# <br>
<br>
root@notosh:/home/ckosloff# cpuid -r<br>
CPU 0:<br>
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x00000001 0x00: eax=0x00730f01 ebx=0x00040800 ecx=0x7ed8220b
edx=0x178bfbff<br>
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000<br>
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000<br>
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000<br>
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000<br>
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff<br>
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041<br>
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65<br>
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020<br>
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140<br>
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000<br>
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9<br>
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000<br>
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf<br>
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000<br>
0x8000001e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
CPU 1:<br>
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x00000001 0x00: eax=0x00730f01 ebx=0x01040800 ecx=0x7ed8220b
edx=0x178bfbff<br>
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000<br>
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000<br>
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000<br>
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000<br>
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff<br>
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041<br>
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65<br>
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020<br>
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140<br>
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000<br>
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9<br>
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000<br>
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf<br>
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000<br>
0x8000001e 0x00: eax=0x00000001 ebx=0x00000001 ecx=0x00000000
edx=0x00000000<br>
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
CPU 2:<br>
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x00000001 0x00: eax=0x00730f01 ebx=0x02040800 ecx=0x7ed8220b
edx=0x178bfbff<br>
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000<br>
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000<br>
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000<br>
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000<br>
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff<br>
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041<br>
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65<br>
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020<br>
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140<br>
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000<br>
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9<br>
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000<br>
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf<br>
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000<br>
0x8000001e 0x00: eax=0x00000002 ebx=0x00000002 ecx=0x00000000
edx=0x00000000<br>
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
CPU 3:<br>
0x00000000 0x00: eax=0x0000000d ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x00000001 0x00: eax=0x00730f01 ebx=0x03040800 ecx=0x7ed8220b
edx=0x178bfbff<br>
0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000005 0x00: eax=0x00000040 ebx=0x00000040 ecx=0x00000003
edx=0x00000000<br>
0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000001
edx=0x00000000<br>
0x00000007 0x00: eax=0x00000000 ebx=0x00000008 ecx=0x00000000
edx=0x00000000<br>
0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x00: eax=0x00000007 ebx=0x00000340 ecx=0x00000340
edx=0x00000000<br>
0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000
edx=0x00000000<br>
0x0000000d 0x3e: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000000 0x00: eax=0x8000001e ebx=0x68747541 ecx=0x444d4163
edx=0x69746e65<br>
0x80000001 0x00: eax=0x00730f01 ebx=0x00000000 ecx=0x1d4037ff
edx=0x2fd3fbff<br>
0x80000002 0x00: eax=0x20444d41 ebx=0x362d3641 ecx=0x20303133
edx=0x20555041<br>
0x80000003 0x00: eax=0x68746977 ebx=0x444d4120 ecx=0x64615220
edx=0x206e6f65<br>
0x80000004 0x00: eax=0x47203452 ebx=0x68706172 ecx=0x20736369
edx=0x00202020<br>
0x80000005 0x00: eax=0xff08ff08 ebx=0xff28ff20 ecx=0x20080140
edx=0x20020140<br>
0x80000006 0x00: eax=0x21000000 ebx=0x42004200 ecx=0x08008140
edx=0x00000000<br>
0x80000007 0x00: eax=0x00000000 ebx=0x00000001 ecx=0x00002800
edx=0x000033d9<br>
0x80000008 0x00: eax=0x00003028 ebx=0x00000000 ecx=0x00003003
edx=0x00000000<br>
0x80000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000a 0x00: eax=0x00000001 ebx=0x00000008 ecx=0x00000000
edx=0x00001cdf<br>
0x8000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000d 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000015 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x80000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001a 0x00: eax=0x00000003 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001b 0x00: eax=0x000000ff ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0x8000001d 0x00: eax=0x00000121 ebx=0x01c0003f ecx=0x0000003f
edx=0x00000000<br>
0x8000001e 0x00: eax=0x00000003 ebx=0x00000003 ecx=0x00000000
edx=0x00000000<br>
0x80860000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
0xc0000000 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000
edx=0x00000000<br>
root@notosh:/home/ckosloff# <br>
<br>
<br>
<br>
<div class="moz-signature"><strong>Carlos Kosloff</strong><br>
Office: (954) 283-8828<br>
Cell: (954) 464-8822<br>
Fax: (888) 854-5440<br>
<hr size="2" width="60%" color="blue"></div>
<div class="moz-cite-prefix">On 07/30/2015 03:20 PM, Kurt Roeckx
wrote:<br>
</div>
<blockquote cite="mid:20150730192052.GB3631@roeckx.be" type="cite">
<pre wrap="">On Thu, Jul 30, 2015 at 02:42:33PM -0400, Carlos Kosloff wrote:
</pre>
<blockquote type="cite">
<pre wrap="">That worked! Thank you.
</pre>
</blockquote>
<pre wrap="">
That's just a workaround that disables the cpu detection code.
Can you try installing cpuid and running:
cpuid
cpuid -r
And send me the output of both those?
Kurt
</pre>
</blockquote>
<br>
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