vdr/xine-lib-vdr/src/video_out/vidix/drivers Makefile.am Makefile.in cyberblade_regs.h cyberblade_vid.c genfb_vid.c glint_regs.h mach64.h mach64_vid.c mga_crtc2_vid.c mga_vid.c nvidia.h nvidia_vid.c pm2_vid.c pm3_regs.h pm3_vid.c radeon.h radeon_vid.c rage128_vid.c sis_bridge.c sis_defs.h sis_regs.h sis_vid.c
Darren Salt
pkg-vdr-dvb-changes@lists.alioth.debian.org
Mon, 04 Apr 2005 22:38:35 +0000
Update of /cvsroot/pkg-vdr-dvb/vdr/xine-lib-vdr/src/video_out/vidix/drivers
In directory haydn:/tmp/cvs-serv13100/src/video_out/vidix/drivers
Added Files:
Makefile.am Makefile.in cyberblade_regs.h cyberblade_vid.c
genfb_vid.c glint_regs.h mach64.h mach64_vid.c mga_crtc2_vid.c
mga_vid.c nvidia.h nvidia_vid.c pm2_vid.c pm3_regs.h pm3_vid.c
radeon.h radeon_vid.c rage128_vid.c sis_bridge.c sis_defs.h
sis_regs.h sis_vid.c
Log Message:
Import of VDR-patched xine-lib.
--- NEW FILE: sis_regs.h ---
/**
SiS register definitions and access macros.
From SiS X11 driver.
Copyright 2001-2003 by Thomas Winischhofer, Vienna, Austria.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
**/
#ifndef VIDIX_SIS_REGS_H
#define VIDIX_SIS_REGS_H
#define inSISREG(base) INPORT8(base)
#define outSISREG(base,val) OUTPORT8(base, val)
#define orSISREG(base,val) do { \
unsigned char __Temp = INPORT8(base); \
outSISREG(base, __Temp | (val)); \
} while (0)
#define andSISREG(base,val) do { \
unsigned char __Temp = INPORT8(base); \
outSISREG(base, __Temp & (val)); \
} while (0)
#define inSISIDXREG(base,idx,var) do { \
OUTPORT8(base, idx); var=INPORT8((base)+1); \
} while (0)
#define outSISIDXREG(base,idx,val) do { \
OUTPORT8(base, idx); OUTPORT8((base)+1, val); \
} while (0)
#define orSISIDXREG(base,idx,val) do { \
unsigned char __Temp; \
OUTPORT8(base, idx); \
__Temp = INPORT8((base)+1)|(val); \
outSISIDXREG(base,idx,__Temp); \
} while (0)
#define andSISIDXREG(base,idx,and) do { \
unsigned char __Temp; \
OUTPORT8(base, idx); \
__Temp = INPORT8((base)+1)&(and); \
outSISIDXREG(base,idx,__Temp); \
} while (0)
#define setSISIDXREG(base,idx,and,or) do { \
unsigned char __Temp; \
OUTPORT8(base, idx); \
__Temp = (INPORT8((base)+1)&(and))|(or); \
outSISIDXREG(base,idx,__Temp); \
} while (0)
#define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))
#define GENMASK(mask) BITMASK(1?mask,0?mask)
#define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask))
#define SETBITS(val,mask) ((val) << (0?mask))
#define SETBIT(n) (1<<(n))
#define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to))
#define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \
GETBITSTR(val,from,to))
#define GETVAR8(var) ((var)&0xFF)
#define SETVAR8(var,val) (var) = GETVAR8(val)
/* #define VGA_RELIO_BASE 0x380 */
#define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */
#define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */
#define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */
#define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */
#define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */
#define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */
#define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */
#define INPUTSTATOFFSET 0x5A
#define PART1OFFSET 0x04
#define PART2OFFSET 0x10
#define PART3OFFSET 0x12
#define PART4OFFSET 0x14
#define PART5OFFSET 0x16
#define VIDEOOFFSET 0x02
#define COLREGOFFSET 0x48
#define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */
#define SISAR SIS_IOBASE + AROFFSET
#define SISARR SIS_IOBASE + ARROFFSET
#define SISGR SIS_IOBASE + GROFFSET
#define SISSR SIS_IOBASE + SROFFSET
#define SISCR SIS_IOBASE + CROFFSET
#define SISMISCR SIS_IOBASE + MISCROFFSET
#define SISMISCW SIS_IOBASE + MISCWOFFSET
#define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET
#define SISPART1 SIS_IOBASE + PART1OFFSET
#define SISPART2 SIS_IOBASE + PART2OFFSET
#define SISPART3 SIS_IOBASE + PART3OFFSET
#define SISPART4 SIS_IOBASE + PART4OFFSET
#define SISPART5 SIS_IOBASE + PART5OFFSET
#define SISVID SIS_IOBASE + VIDEOOFFSET
#define SISCOLIDX SIS_IOBASE + COLREGOFFSET
#define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1
#define SISCOL2IDX SISPART5
#define SISCOL2DATA SISPART5 + 1
#define vc_index_offset 0x00 /* Video capture - unused */
#define vc_data_offset 0x01
#define vi_index_offset VIDEOOFFSET
#define vi_data_offset (VIDEOOFFSET + 1)
#define crt2_index_offset PART1OFFSET
#define crt2_port_offset (PART1OFFSET + 1)
#define sr_index_offset SROFFSET
#define sr_data_offset (SROFFSET + 1)
#define cr_index_offset CROFFSET
#define cr_data_offset (CROFFSET + 1)
#define input_stat INPUTSTATOFFSET
/* For old chipsets (5597/5598, 6326, 530/620) ------------ */
/* SR (3C4) */
#define BankReg 0x06
#define ClockReg 0x07
#define CPUThreshold 0x08
#define CRTThreshold 0x09
#define CRTCOff 0x0A
#define DualBanks 0x0B
#define MMIOEnable 0x0B
#define RAMSize 0x0C
#define Mode64 0x0C
#define ExtConfStatus1 0x0E
#define ClockBase 0x13
#define LinearAdd0 0x20
#define LinearAdd1 0x21
#define GraphEng 0x27
#define MemClock0 0x28
#define MemClock1 0x29
#define XR2A 0x2A
#define XR2B 0x2B
#define TurboQueueBase 0x2C
#define FBSize 0x2F
#define ExtMiscCont5 0x34
#define ExtMiscCont9 0x3C
/* 3x4 */
#define Offset 0x13
/* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */
/* VGA standard register */
#define Index_SR_Graphic_Mode 0x06
#define Index_SR_RAMDAC_Ctrl 0x07
#define Index_SR_Threshold_Ctrl1 0x08
#define Index_SR_Threshold_Ctrl2 0x09
#define Index_SR_Misc_Ctrl 0x0F
#define Index_SR_DDC 0x11
#define Index_SR_Feature_Connector_Ctrl 0x12
#define Index_SR_DRAM_Sizing 0x14
#define Index_SR_DRAM_State_Machine_Ctrl 0x15
#define Index_SR_AGP_PCI_State_Machine 0x21
#define Index_SR_Internal_MCLK0 0x28
#define Index_SR_Internal_MCLK1 0x29
#define Index_SR_Internal_DCLK1 0x2B
#define Index_SR_Internal_DCLK2 0x2C
#define Index_SR_Internal_DCLK3 0x2D
#define Index_SR_Ext_Clock_Sel 0x32
#define Index_SR_Int_Status 0x34
#define Index_SR_Int_Enable 0x35
#define Index_SR_Int_Reset 0x36
#define Index_SR_Power_On_Trap 0x38
#define Index_SR_Power_On_Trap2 0x39
#define Index_SR_Power_On_Trap3 0x3A
/* video registers (300/630/730/315/550/650/740 only) */
#define Index_VI_Passwd 0x00
/* Video overlay horizontal start/end, unit=screen pixels */
#define Index_VI_Win_Hor_Disp_Start_Low 0x01
#define Index_VI_Win_Hor_Disp_End_Low 0x02
#define Index_VI_Win_Hor_Over 0x03 /* Overflow */
/* Video overlay vertical start/end, unit=screen pixels */
#define Index_VI_Win_Ver_Disp_Start_Low 0x04
#define Index_VI_Win_Ver_Disp_End_Low 0x05
#define Index_VI_Win_Ver_Over 0x06 /* Overflow */
/* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */
#define Index_VI_Disp_Y_Buf_Start_Low 0x07
#define Index_VI_Disp_Y_Buf_Start_Middle 0x08
#define Index_VI_Disp_Y_Buf_Start_High 0x09
/* U Plane (4:2:0) buffer start address, unit=word */
#define Index_VI_U_Buf_Start_Low 0x0A
#define Index_VI_U_Buf_Start_Middle 0x0B
#define Index_VI_U_Buf_Start_High 0x0C
/* V Plane (4:2:0) buffer start address, unit=word */
#define Index_VI_V_Buf_Start_Low 0x0D
#define Index_VI_V_Buf_Start_Middle 0x0E
#define Index_VI_V_Buf_Start_High 0x0F
/* Pitch for Y, UV Planes, unit=word */
#define Index_VI_Disp_Y_Buf_Pitch_Low 0x10
#define Index_VI_Disp_UV_Buf_Pitch_Low 0x11
#define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12
/* What is this ? */
#define Index_VI_Disp_Y_Buf_Preset_Low 0x13
#define Index_VI_Disp_Y_Buf_Preset_Middle 0x14
#define Index_VI_UV_Buf_Preset_Low 0x15
#define Index_VI_UV_Buf_Preset_Middle 0x16
#define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17
/* Scaling control registers */
#define Index_VI_Hor_Post_Up_Scale_Low 0x18
#define Index_VI_Hor_Post_Up_Scale_High 0x19
#define Index_VI_Ver_Up_Scale_Low 0x1A
#define Index_VI_Ver_Up_Scale_High 0x1B
#define Index_VI_Scale_Control 0x1C
/* Playback line buffer control */
#define Index_VI_Play_Threshold_Low 0x1D
#define Index_VI_Play_Threshold_High 0x1E
#define Index_VI_Line_Buffer_Size 0x1F
/* Destination color key */
#define Index_VI_Overlay_ColorKey_Red_Min 0x20
#define Index_VI_Overlay_ColorKey_Green_Min 0x21
#define Index_VI_Overlay_ColorKey_Blue_Min 0x22
#define Index_VI_Overlay_ColorKey_Red_Max 0x23
#define Index_VI_Overlay_ColorKey_Green_Max 0x24
#define Index_VI_Overlay_ColorKey_Blue_Max 0x25
/* Source color key, YUV color space */
#define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26
#define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27
#define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28
#define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29
#define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A
#define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B
/* Contrast enhancement and brightness control */
#define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */
#define Index_VI_Brightness 0x2D
#define Index_VI_Contrast_Enh_Ctrl 0x2E
#define Index_VI_Key_Overlay_OP 0x2F
#define Index_VI_Control_Misc0 0x30
#define Index_VI_Control_Misc1 0x31
#define Index_VI_Control_Misc2 0x32
/* TW: Subpicture registers */
#define Index_VI_SubPict_Buf_Start_Low 0x33
#define Index_VI_SubPict_Buf_Start_Middle 0x34
#define Index_VI_SubPict_Buf_Start_High 0x35
/* TW: What is this ? */
#define Index_VI_SubPict_Buf_Preset_Low 0x36
#define Index_VI_SubPict_Buf_Preset_Middle 0x37
/* TW: Subpicture pitch, unit=16 bytes */
#define Index_VI_SubPict_Buf_Pitch 0x38
/* TW: Subpicture scaling control */
#define Index_VI_SubPict_Hor_Scale_Low 0x39
#define Index_VI_SubPict_Hor_Scale_High 0x3A
#define Index_VI_SubPict_Vert_Scale_Low 0x3B
#define Index_VI_SubPict_Vert_Scale_High 0x3C
#define Index_VI_SubPict_Scale_Control 0x3D
/* (0x40 = enable/disable subpicture) */
/* TW: Subpicture line buffer control */
#define Index_VI_SubPict_Threshold 0x3E
/* TW: What is this? */
#define Index_VI_FIFO_Max 0x3F
/* TW: Subpicture palette; 16 colors, total 32 bytes address space */
#define Index_VI_SubPict_Pal_Base_Low 0x40
#define Index_VI_SubPict_Pal_Base_High 0x41
/* I wish I knew how to use these ... */
#define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */
#define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */
#define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */
#define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */
/* TW: MPEG AutoFlip scale */
#define Index_MPEG_Ver_Up_Scale_Low 0x64
#define Index_MPEG_Ver_Up_Scale_High 0x65
#define Index_MPEG_Y_Buf_Preset_Low 0x66
#define Index_MPEG_Y_Buf_Preset_Middle 0x67
#define Index_MPEG_UV_Buf_Preset_Low 0x68
#define Index_MPEG_UV_Buf_Preset_Middle 0x69
#define Index_MPEG_Y_UV_Buf_Preset_High 0x6A
/* TW: The following registers only exist on the 310/325 series */
/* TW: Bit 16:24 of Y_U_V buf start address (?) */
#define Index_VI_Y_Buf_Start_Over 0x6B
#define Index_VI_U_Buf_Start_Over 0x6C
#define Index_VI_V_Buf_Start_Over 0x6D
#define Index_VI_Disp_Y_Buf_Pitch_High 0x6E
#define Index_VI_Disp_UV_Buf_Pitch_High 0x6F
/* Hue and saturation */
#define Index_VI_Hue 0x70
#define Index_VI_Saturation 0x71
#define Index_VI_SubPict_Start_Over 0x72
#define Index_VI_SubPict_Buf_Pitch_High 0x73
#define Index_VI_Control_Misc3 0x74
/* TW: Bits (and helpers) for Index_VI_Control_Misc0 */
#define VI_Misc0_Enable_Overlay 0x02
#define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */
#define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */
#define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */
#define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */
#define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */
/* TW: Bits for Index_VI_Control_Misc1 */
/* #define VI_Misc1_? 0x01 */
#define VI_Misc1_BOB_Enable 0x02
#define VI_Misc1_Line_Merge 0x04
#define VI_Misc1_Field_Mode 0x08
/* #define VI_Misc1_? 0x10 */
#define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */
#define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */
/* #define VI_Misc1_? 0x40 */
/* #define VI_Misc1_? 0x80 */
/* TW: Bits for Index_VI_Control_Misc2 */
#define VI_Misc2_Select_Video2 0x01
#define VI_Misc2_Video2_On_Top 0x02
/* #define VI_Misc2_? 0x04 */
#define VI_Misc2_Vertical_Interpol 0x08
#define VI_Misc2_Dual_Line_Merge 0x10
#define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */
#define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */
#define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */
/* TW: Bits for Index_VI_Control_Misc3 */
#define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */
#define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */
#define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */
/* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */
#define VI_ROP_Never 0x00
#define VI_ROP_DestKey 0x03
#define VI_ROP_Always 0x0F
/*
* CRT_2 function control register ---------------------------------
*/
#define Index_CRT2_FC_CONTROL 0x00
#define Index_CRT2_FC_SCREEN_HIGH 0x04
#define Index_CRT2_FC_SCREEN_MID 0x05
#define Index_CRT2_FC_SCREEN_LOW 0x06
#define Index_CRT2_FC_ENABLE_WRITE 0x24
#define Index_CRT2_FC_VR 0x25
#define Index_CRT2_FC_VCount 0x27
#define Index_CRT2_FC_VCount1 0x28
#define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */
#define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */
/* video attributes - these should probably be configurable on the fly
* so users with different desktop sizes can keep
* captured data off the desktop
*/
#define _VINWID 704
#define _VINHGT _VINHGT_NTSC
#define _VINHGT_NTSC 240
#define _VINHGT_PAL 290
#define _VIN_WINDOW (704 * 291 * 2)
#define _VBI_WINDOW (704 * 64 * 2)
#define _VIN_FIELD_EVEN 1
#define _VIN_FIELD_ODD 2
#define _VIN_FIELD_BOTH 4
/* i2c registers (TW; not on 300/310/325 series) */
#define X_INDEXREG 0x14
#define X_PORTREG 0x15
#define X_DATA 0x0f
#define I2C_SCL 0x00
#define I2C_SDA 0x01
#define I2C_DELAY 10
/* mmio registers for video */
#define REG_PRIM_CRT_COUNTER 0x8514
/* TW: MPEG MMIO registers (630 and later) ----------------------------*/
/* Not public (yet?) */
#endif /* VIDIX_SIS_REGS_H */
--- NEW FILE: mga_crtc2_vid.c ---
/*
* Matrox MGA driver
*
* ported to VIDIX by Alex Beregszaszi
*
* YUY2 support (see config.format) added by A'rpi/ESP-team
* double buffering added by A'rpi/ESP-team
*
* Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me
*
* Fixed Brightness/Contrast
* Rewrite or read/write kabi@users.sf.net
*
* TODO:
* * fix memory size detection (current reading pci userconfig isn't
* working as requested - returns the max avail. ram on arch?)
* * translate all non-english comments to english
*/
[...1493 lines suppressed...]
int VIDIX_NAME(vixPlaybackGetEq)( vidix_video_eq_t * eq)
{
float factor = 2000.0 / 255;
/* contrast and brightness control isn't supported on G200 - alex */
if (!is_g400)
{
if (mga_verbose) printf(MGA_MSG" equalizer isn't supported with G200\n");
return(ENOTSUP);
}
// BESLUMACTL is WO only registr!
// this will not work: regs.beslumactl = readl(BESLUMACTL);
eq->brightness = ((signed char)((regs.beslumactl >> 16) & 0xff)) * factor;
eq->contrast = (regs.beslumactl & 0xFF) * factor - 1000;
eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST;
return(0);
}
--- NEW FILE: mga_vid.c ---
/*
* Matrox MGA driver
*
* ported to VIDIX by Alex Beregszaszi
*
* YUY2 support (see config.format) added by A'rpi/ESP-team
* double buffering added by A'rpi/ESP-team
*
* Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me
*
* Fixed Brightness/Contrast
* Rewrite or read/write kabi@users.sf.net
*
* TODO:
* * fix memory size detection (current reading pci userconfig isn't
* working as requested - returns the max avail. ram on arch?)
* * translate all non-english comments to english
*/
[...1493 lines suppressed...]
int VIDIX_NAME(vixPlaybackGetEq)( vidix_video_eq_t * eq)
{
float factor = 2000.0 / 255;
/* contrast and brightness control isn't supported on G200 - alex */
if (!is_g400)
{
if (mga_verbose) printf(MGA_MSG" equalizer isn't supported with G200\n");
return(ENOTSUP);
}
// BESLUMACTL is WO only registr!
// this will not work: regs.beslumactl = readl(BESLUMACTL);
eq->brightness = ((signed char)((regs.beslumactl >> 16) & 0xff)) * factor;
eq->contrast = (regs.beslumactl & 0xFF) * factor - 1000;
eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST;
return(0);
}
--- NEW FILE: Makefile.am ---
include $(top_srcdir)/misc/Makefile.common
EXTRA_DIST = genfb_vid.c nvidia_vid.c
libdir = $(XINE_PLUGINDIR)/vidix
if HAVE_VIDIX
vidix_drivers = \
mach64_vid.la \
mga_crtc2_vid.la \
mga_vid.la \
pm2_vid.la \
pm3_vid.la \
radeon_vid.la \
rage128_vid.la \
cyberblade_vid.la \
sis_vid.la
endif
lib_LTLIBRARIES = $(vidix_drivers)
radeon_vid_la_SOURCES = radeon_vid.c
radeon_vid_la_LIBADD = -lm
radeon_vid_la_LDFLAGS = -avoid-version -module
rage128_vid.c:
@echo "$(LN_S) -f $(top_srcdir)/src/video_out/vidix/drivers/radeon_vid.c \
$(top_builddir)/src/video_out/vidix/drivers/$*.c"; \
$(LN_S) -f $(top_srcdir)/src/video_out/vidix/drivers/radeon_vid.c \
$(top_builddir)/src/video_out/vidix/drivers/$*.c
rage128_vid.lo: $(rage128_vid_la_SOURCES)
source='$*.c' object='$@' libtool=yes \
depfile='$(DEPDIR)/$*.Plo' tmpdepfile='$(DEPDIR)/$*.TPlo' \
$(CCDEPMODE) $(depcomp) \
$(LTCOMPILE) -DRAGE128 -c -o $@ `test -f $*.c || echo '$(srcdir)/'`$*.c
rage128_vid_la_SOURCES = rage128_vid.c
rage128_vid_la_LDFLAGS = -avoid-version -module
pm2_vid_la_SOURCES = pm2_vid.c
pm2_vid_la_LDFLAGS = -avoid-version -module
pm3_vid_la_SOURCES = pm3_vid.c
pm3_vid_la_LDFLAGS = -avoid-version -module
mach64_vid.lo:
source='$*.c' object='$@' libtool=yes \
depfile='$(DEPDIR)/$*.Plo' tmpdepfile='$(DEPDIR)/$*.TPlo' \
$(CCDEPMODE) $(depcomp) \
$(LTCOMPILE) -c -o $@ `test -f $*.c || echo '$(srcdir)/'`$*.c
mach64_vid_la_SOURCES = mach64_vid.c
mach64_vid_la_LDFLAGS = -avoid-version -module
mga_vid_la_SOURCES = mga_vid.c
mga_vid_la_LIBADD = -lm
mga_vid_la_LDFLAGS = -avoid-version -module
mga_crtc2_vid.c:
@echo "$(LN_S) -f $(top_srcdir)/src/video_out/vidix/drivers/mga_vid.c \
$(top_builddir)/src/video_out/vidix/drivers/$*.c"; \
$(LN_S) -f $(top_srcdir)/src/video_out/vidix/drivers/mga_vid.c \
$(top_builddir)/src/video_out/vidix/drivers/$*.c
mga_crtc2_vid.lo: $(mga_crtc2_vid_la_SOURCES)
source='$*.c' object='$@' libtool=yes \
depfile='$(DEPDIR)/$*.Plo' tmpdepfile='$(DEPDIR)/$*.TPlo' \
$(CCDEPMODE) $(depcomp) \
$(LTCOMPILE) -DCRTC2 -c -o $@ `test -f $*.c || echo '$(srcdir)/'`$*.c
mga_crtc2_vid_la_SOURCES = mga_crtc2_vid.c
mga_crtc2_vid_la_LIBADD = -lm
mga_crtc2_vid_la_LDFLAGS = -avoid-version -module
cyberblade_vid_la_SOURCES = cyberblade_vid.c
cyberblade_vid_la_LDFLAGS = -avoid-version -module
sis_vid_la_SOURCES = sis_vid.c sis_bridge.c
sis_vid_la_LDFLAGS = -avoid-version -module
noinst_HEADERS = mach64.h nvidia.h glint_regs.h pm3_regs.h radeon.h \
cyberblade_regs.h sis_defs.h sis_regs.h
AM_CPPFLAGS = -I$(top_srcdir)/src/video_out/vidix \
-I$(top_srcdir)/src/video_out/libdha \
-I$(top_builddir)/src/video_out/libdha
--- NEW FILE: nvidia.h ---
#include <inttypes.h>
#define RIVA_FIFO_FREE(hwptr, cnt) \
{ \
while (nv_fifo_space < (cnt)) { \
nv_fifo_space = hwptr->fifo_free >> 2; \
} \
nv_fifo_space -= (cnt); \
}
typedef struct {
uint32_t reserved00[4];
uint16_t fifo_free;
uint16_t nop[1];
uint32_t reserved01[0x03b];
uint32_t no_operation;
uint32_t notify;
uint32_t reserved02[0x01e];
uint32_t set_context_dma_notifies;
uint32_t set_context_dma_image;
uint32_t set_context_pattern;
uint32_t set_context_rop;
uint32_t set_context_beta1;
uint32_t set_context_surface;
uint32_t reserved03[0x05a];
uint32_t set_color_format;
uint32_t set_operation;
int16_t clip_x;
int16_t clip_y;
uint16_t clip_height;
uint16_t clip_width;
int16_t image_out_x;
int16_t image_out_y;
uint16_t image_out_height;
uint16_t image_out_width;
uint32_t du_dx;
uint32_t du_dy;
uint32_t reserved04[0x38];
uint16_t image_in_height;
uint16_t image_in_width;
uint32_t image_in_format;
uint32_t image_in_offset;
uint32_t image_in_point;
uint32_t reserved05[0x6fc];
} RivaScaledImage;
#define dump_scaledimage(x) { \
printf("clip: pos: %dx%d, size: %dx%d\n", \
x->clip_x, x->clip_y, x->clip_height, x->clip_width); \
printf("image_out: pos: %dx%d, size: %dx%d\n", \
x->image_out_x, x->image_out_y, x->image_out_height, x->image_out_width); \
printf("image_in: size: %dx%d format: %x offset: %x\n", \
x->image_in_height, x->image_in_width, x->image_in_format, x->image_in_offset); \
}
--- NEW FILE: mach64_vid.c ---
/*
mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips
Copyrights 2002 Nick Kurshev. This file is based on sources from
GATOS (gatos.sf.net) and X11 (www.xfree86.org)
Licence: GPL
WARNING: THIS DRIVER IS IN BETTA STAGE
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <inttypes.h>
#include <fcntl.h>
#include <limits.h>
#include <sys/mman.h> /* for m(un)lock */
#ifdef HAVE_MALLOC_H
#include <malloc.h>
#ifdef HAVE_MEMALIGN
[...1353 lines suppressed...]
int retval,sync_mode;
if(!(dmai->flags & BM_DMA_FIXED_BUFFS)) if(bm_lock_mem(dmai->src,dmai->size) != 0) return errno;
sync_mode = (dmai->flags & BM_DMA_SYNC) == BM_DMA_SYNC;
if(sync_mode)
{
if(!irq_installed) init_irq();
/* burn CPU instead of PCI bus here */
while(vixQueryDMAStatus()!=0){
if(can_use_irq) hwirq_wait(pci_info.irq);
else usleep(0); /* ugly but may help */
}
}
mach64_engine_reset();
retval = mach64_setup_frame(dmai);
VIRT_TO_CARD(mach64_dma_desc_base[dmai->idx],1,&bus_addr_dma_desc);
if(retval == 0) retval = mach64_transfer_frame(bus_addr_dma_desc,sync_mode);
if(!(dmai->flags & BM_DMA_FIXED_BUFFS)) bm_unlock_mem(dmai->src,dmai->size);
return retval;
}
#endif
--- NEW FILE: radeon.h ---
/*
* radeon.h
* This software has been released under the terms of the GNU Public
* license. See http://www.gnu.org/copyleft/gpl.html for details.
*
* This collection of definition was written by Nick Kurshev
* It's based on radeonfb, X11, GATOS sources
* and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts)
*/
#ifndef _RADEON_H
#define _RADEON_H
#define RADEON_REGSIZE 0x4000
#define MM_INDEX 0x0000
/* MM_INDEX bit constants */
# define MM_APER 0x80000000
#define MM_DATA 0x0004
#define BUS_CNTL 0x0030
[...2182 lines suppressed...]
#define fld_ADC_PREFHI_def 0x00000000
#define fld_ADC_CH_GAIN_SEL_def 0x00000001
#define fld_HS_PLL_SGAIN_def 0x00000003
#define fld_NREn_def 0x00000000
#define fld_NRGainCntl_def 0x00000000
#define fld_NRBWTresh_def 0x00000000
#define fld_NRGCTresh_def 0x00000000
#define fld_NRCoefDespeclMode_def 0x00000000
#define fld_GPIO_5_OE_def 0x00000000
#define fld_GPIO_6_OE_def 0x00000000
#define fld_GPIO_5_OUT_def 0x00000000
#define fld_GPIO_6_OUT_def 0x00000000
/* End of field default values. */
#endif /* RADEON_H */
--- NEW FILE: rage128_vid.c ---
/*
radeon_vid - VIDIX based video driver for Radeon and Rage128 chips
Copyrights 2002 Nick Kurshev. This file is based on sources from
GATOS (gatos.sf.net) and X11 (www.xfree86.org)
Licence: GPL
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <inttypes.h>
#include <sys/types.h>
#include <sys/mman.h>
#include "bswap.h"
#include "pci_ids.h"
#include "pci_names.h"
#include "vidix.h"
[...3309 lines suppressed...]
{
int retval;
if(mlock(dmai->src,dmai->size) != 0) return errno;
retval = radeon_setup_frame(dmai);
if(retval == 0) retval = radeon_transfer_frame();
munlock(dmai->src,dmai->size);
return retval;
}
int VIDIX_NAME(vixQueryDMAStatus)( void )
{
int bm_active;
#if 1 //def RAGE128
bm_active=(INREG(GEN_INT_STATUS)&0x00010000)==0?1:0;
#else
bm_active=(INREG(GEN_INT_STATUS)&(1<<30))==0?1:0;
#endif
return bm_active?1:0;
}
#endif
--- NEW FILE: genfb_vid.c ---
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <inttypes.h>
#include <fcntl.h>
#include "../vidix.h"
#include "../fourcc.h"
#include "../../libdha/libdha.h"
#include "../../libdha/pci_ids.h"
#include "../../libdha/pci_names.h"
#define DEMO_DRIVER 1
#define VIDIX_STATIC genfb_
#define GENFB_MSG "[genfb-demo-driver] "
#if 0 /* these are unused. remove? */
static int fd;
static void *mmio_base = 0;
static void *mem_base = 0;
static int32_t overlay_offset = 0;
static uint32_t ram_size = 0;
#endif
static int probed = 0;
/* VIDIX exports */
static vidix_capability_t genfb_cap =
{
"General Framebuffer",
"alex",
TYPE_OUTPUT,
{ 0, 0, 0, 0 },
2048,
2048,
4,
4,
-1,
FLAG_UPSCALER|FLAG_DOWNSCALER,
-1,
-1,
{ 0, 0, 0, 0 }
};
unsigned int VIDIX_NAME(vixGetVersion)(void)
{
return(VIDIX_VERSION);
}
int VIDIX_NAME(vixProbe)(int verbose,int force)
{
#if 0
int err = 0;
#ifdef DEMO_DRIVER
err = ENOSYS;
#endif
printf(GENFB_MSG"probe\n");
fd = open("/dev/fb0", O_RDWR);
if (fd < 0)
{
printf(GENFB_MSG"Error occured durint open: %s\n", strerror(errno));
err = errno;
}
probed = 1;
return(err);
#else
pciinfo_t lst[MAX_PCI_DEVICES];
unsigned i,num_pci;
int err;
err = pci_scan(lst,&num_pci);
if(err)
{
printf(GENFB_MSG"Error occured during pci scan: %s\n",strerror(err));
return err;
}
else
{
err = ENXIO;
for(i=0;i<num_pci;i++)
{
if(verbose)
printf(GENFB_MSG" Found chip [%04X:%04X] '%s' '%s'\n"
,lst[i].vendor
,lst[i].device
,pci_vendor_name(lst[i].vendor)
,pci_device_name(lst[i].vendor,lst[i].device));
}
}
return ENOSYS;
#endif
}
int VIDIX_NAME(vixInit)(const char *args)
{
printf(GENFB_MSG"init\n");
if (!probed)
{
printf(GENFB_MSG"Driver was not probed but is being initialized\n");
return(EINTR);
}
return(0);
}
void VIDIX_NAME(vixDestroy)(void)
{
printf(GENFB_MSG"destory\n");
return;
}
int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to)
{
memcpy(to, &genfb_cap, sizeof(vidix_capability_t));
return(0);
}
int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to)
{
printf(GENFB_MSG"query fourcc (%x)\n", to->fourcc);
to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
VID_DEPTH_4BPP | VID_DEPTH_8BPP |
VID_DEPTH_12BPP | VID_DEPTH_15BPP |
VID_DEPTH_16BPP | VID_DEPTH_24BPP |
VID_DEPTH_32BPP;
to->flags = 0;
return(0);
}
int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info)
{
printf(GENFB_MSG"config playback\n");
info->num_frames = 2;
info->frame_size = info->src.w*info->src.h+(info->src.w*info->src.h)/2;
info->dest.pitch.y = 32;
info->dest.pitch.u = info->dest.pitch.v = 16;
info->offsets[0] = 0;
info->offsets[1] = info->frame_size;
info->offset.y = 0;
info->offset.v = ((info->src.w+31) & ~31) * info->src.h;
info->offset.u = info->offset.v+((info->src.w+31) & ~31) * info->src.h/4;
info->dga_addr = malloc(info->num_frames*info->frame_size);
printf(GENFB_MSG"frame_size: %d, dga_addr: %p\n",
info->frame_size, info->dga_addr);
return(0);
}
int VIDIX_NAME(vixPlaybackOn)(void)
{
printf(GENFB_MSG"playback on\n");
return(0);
}
int VIDIX_NAME(vixPlaybackOff)(void)
{
printf(GENFB_MSG"playback off\n");
return(0);
}
int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned int frame)
{
printf(GENFB_MSG"frameselect: %d\n", frame);
return(0);
}
--- NEW FILE: sis_bridge.c ---
/**
Video bridge detection for SiS 300 and 310/325 series chips.
Copyright 2003 Jake Page, Sugar Media.
Based on SiS Xv driver:
Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
**/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include "libdha.h"
#include "sis_regs.h"
#include "sis_defs.h"
void sis_init_video_bridge(void);
static void sis_ddc2_delay(unsigned short delaytime)
{
unsigned short i;
int temp;
for (i = 0; i < delaytime; i++) {
inSISIDXREG(SISSR, 0x05, temp);
}
}
static int sis_do_sense(int tempbl, int tempbh, int tempcl, int tempch)
{
int temp;
outSISIDXREG(SISPART4, 0x11, tempbl);
temp = tempbh | tempcl;
setSISIDXREG(SISPART4, 0x10, 0xe0, temp);
//usleep(200000);
sis_ddc2_delay(0x1000);
tempch &= 0x7f;
inSISIDXREG(SISPART4, 0x03, temp);
temp ^= 0x0e;
temp &= tempch;
return (temp == tempch);
}
/* sense connected devices on 30x bridge */
static void sis_sense_30x()
{
unsigned char backupP4_0d, backupP2_00, biosflag;
unsigned char testsvhs_tempbl, testsvhs_tempbh;
unsigned char testsvhs_tempcl, testsvhs_tempch;
unsigned char testcvbs_tempbl, testcvbs_tempbh;
unsigned char testcvbs_tempcl, testcvbs_tempch;
unsigned char testvga2_tempbl, testvga2_tempbh;
unsigned char testvga2_tempcl, testvga2_tempch;
int myflag, result = 0, i, j, haveresult;
#if 0
unsigned short temp;
#endif
inSISIDXREG(SISPART4, 0x0d, backupP4_0d);
outSISIDXREG(SISPART4, 0x0d, (backupP4_0d | 0x04));
inSISIDXREG(SISPART2, 0x00, backupP2_00);
outSISIDXREG(SISPART2, 0x00, (backupP2_00 | 0x1c));
sis_do_sense(0, 0, 0, 0);
if ((sis_vga_engine == SIS_315_VGA) ||
(sis_device_id == DEVICE_SIS_300)) {
#if 0
if (0 /*pSiS->sishw_ext.UseROM */ ) {
if (sis_vga_engine == SIS_300_VGA)
temp = 0xfe;
else {
temp = 0xf3;
if (sis_device_id == DEVICE_SIS_330)
temp = 0x11b;
}
if (pSiS->BIOS[temp] & 0x08) {
if (sis_verbose > 1) {
printf
("[SiS] SiS30x: Video bridge has DVI-I TMDS/VGA combo connector\n");
}
orSISIDXREG(SISCR, 0x32, 0x80);
} else {
andSISIDXREG(SISCR, 0x32, 0x7f);
}
}
#endif
}
if (sis_vga_engine == SIS_300_VGA) {
if (0 /*pSiS->sishw_ext.UseROM */ ) {
#if 0
testvga2_tempbh = pSiS->BIOS[0xf9];
testvga2_tempbl = pSiS->BIOS[0xf8];
testsvhs_tempbh = pSiS->BIOS[0xfb];
testsvhs_tempbl = pSiS->BIOS[0xfa];
testcvbs_tempbh = pSiS->BIOS[0xfd];
testcvbs_tempbl = pSiS->BIOS[0xfc];
biosflag = pSiS->BIOS[0xfe];
#endif
} else {
testvga2_tempbh = 0x00;
testvga2_tempbl = 0xd1;
testsvhs_tempbh = 0x00;
testsvhs_tempbl = 0xb9;
testcvbs_tempbh = 0x00;
testcvbs_tempbl = 0xb3;
biosflag = 0;
}
if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) {
testvga2_tempbh = 0x01;
testvga2_tempbl = 0x90;
testsvhs_tempbh = 0x01;
testsvhs_tempbl = 0x6b;
testcvbs_tempbh = 0x01;
testcvbs_tempbl = 0x74;
}
inSISIDXREG(SISPART4, 0x01, myflag);
if (myflag & 0x04) {
testvga2_tempbh = 0x00;
testvga2_tempbl = 0xfd;
testsvhs_tempbh = 0x00;
testsvhs_tempbl = 0xdd;
testcvbs_tempbh = 0x00;
testcvbs_tempbl = 0xee;
}
testvga2_tempch = 0x0e;
testvga2_tempcl = 0x08;
testsvhs_tempch = 0x06;
testsvhs_tempcl = 0x04;
testcvbs_tempch = 0x08;
testcvbs_tempcl = 0x04;
if (sis_device_id == DEVICE_SIS_300) {
inSISIDXREG(SISSR, 0x3b, myflag);
if (!(myflag & 0x01)) {
testvga2_tempbh = 0x00;
testvga2_tempbl = 0x00;
testvga2_tempch = 0x00;
testvga2_tempcl = 0x00;
}
}
} else {
if (0 /*pSiS->sishw_ext.UseROM */ ) {
#if 0
if (sis_device_id == DEVICE_SIS_330) {
testvga2_tempbh = pSiS->BIOS[0xe6];
testvga2_tempbl = pSiS->BIOS[0xe5];
testsvhs_tempbh = pSiS->BIOS[0xe8];
testsvhs_tempbl = pSiS->BIOS[0xe7];
testcvbs_tempbh = pSiS->BIOS[0xea];
testcvbs_tempbl = pSiS->BIOS[0xe9];
biosflag = pSiS->BIOS[0x11b];
} else {
testvga2_tempbh = pSiS->BIOS[0xbe];
testvga2_tempbl = pSiS->BIOS[0xbd];
testsvhs_tempbh = pSiS->BIOS[0xc0];
testsvhs_tempbl = pSiS->BIOS[0xbf];
testcvbs_tempbh = pSiS->BIOS[0xc2];
testcvbs_tempbl = pSiS->BIOS[0xc1];
biosflag = pSiS->BIOS[0xf3];
}
#endif
} else {
testvga2_tempbh = 0x00;
testvga2_tempbl = 0xd1;
testsvhs_tempbh = 0x00;
testsvhs_tempbl = 0xb9;
testcvbs_tempbh = 0x00;
testcvbs_tempbl = 0xb3;
biosflag = 0;
}
if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) {
if (0 /*pSiS->sishw_ext.UseROM */ ) {
#if 0
if (sis_device_id == DEVICE_SIS_330) {
testvga2_tempbh = pSiS->BIOS[0xec];
testvga2_tempbl = pSiS->BIOS[0xeb];
testsvhs_tempbh = pSiS->BIOS[0xee];
testsvhs_tempbl = pSiS->BIOS[0xed];
testcvbs_tempbh = pSiS->BIOS[0xf0];
testcvbs_tempbl = pSiS->BIOS[0xef];
} else {
testvga2_tempbh = pSiS->BIOS[0xc4];
testvga2_tempbl = pSiS->BIOS[0xc3];
testsvhs_tempbh = pSiS->BIOS[0xc6];
testsvhs_tempbl = pSiS->BIOS[0xc5];
testcvbs_tempbh = pSiS->BIOS[0xc8];
testcvbs_tempbl = pSiS->BIOS[0xc7];
}
#endif
} else {
if (sis_vbflags & (VB_301B | VB_302B)) {
testvga2_tempbh = 0x01;
testvga2_tempbl = 0x90;
testsvhs_tempbh = 0x01;
testsvhs_tempbl = 0x6b;
testcvbs_tempbh = 0x01;
testcvbs_tempbl = 0x74;
} else {
testvga2_tempbh = 0x00;
testvga2_tempbl = 0x00;
testsvhs_tempbh = 0x02;
testsvhs_tempbl = 0x00;
testcvbs_tempbh = 0x01;
testcvbs_tempbl = 0x00;
}
}
}
if (sis_vbflags & (VB_301 | VB_301B | VB_302B)) {
inSISIDXREG(SISPART4, 0x01, myflag);
if (myflag & 0x04) {
testvga2_tempbh = 0x00;
testvga2_tempbl = 0xfd;
testsvhs_tempbh = 0x00;
testsvhs_tempbl = 0xdd;
testcvbs_tempbh = 0x00;
testcvbs_tempbl = 0xee;
}
}
if (sis_vbflags & (VB_301LV | VB_302LV)) {
/* TW: No VGA2 or SCART on LV bridges */
testvga2_tempbh = 0x00;
testvga2_tempbl = 0x00;
testvga2_tempch = 0x00;
testvga2_tempcl = 0x00;
testsvhs_tempch = 0x04;
testsvhs_tempcl = 0x08;
testcvbs_tempch = 0x08;
testcvbs_tempcl = 0x08;
} else {
testvga2_tempch = 0x0e;
testvga2_tempcl = 0x08;
testsvhs_tempch = 0x06;
testsvhs_tempcl = 0x04;
testcvbs_tempch = 0x08;
testcvbs_tempcl = 0x04;
}
}
/* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x14); */
/* pSiS->postVBCR32 &= ~0x14; */
/* scan for VGA2/SCART */
if (testvga2_tempch || testvga2_tempcl ||
testvga2_tempbh || testvga2_tempbl) {
haveresult = 0;
for (j = 0; j < 10; j++) {
result = 0;
for (i = 0; i < 3; i++) {
if (sis_do_sense(testvga2_tempbl, testvga2_tempbh,
testvga2_tempcl, testvga2_tempch))
result++;
}
if ((result == 0) || (result >= 2))
break;
}
if (result) {
if (biosflag & 0x01) {
if (sis_verbose > 1) {
printf
("[SiS] SiS30x: Detected TV connected to SCART output\n");
}
sis_vbflags |= TV_SCART;
orSISIDXREG(SISCR, 0x32, 0x04);
/*pSiS->postVBCR32 |= 0x04; */
} else {
if (sis_verbose > 1) {
printf
("[SiS] SiS30x: Detected secondary VGA connection\n");
}
sis_vbflags |= VGA2_CONNECTED;
orSISIDXREG(SISCR, 0x32, 0x10);
/*pSiS->postVBCR32 |= 0x10; */
}
}
}
/* scanning for TV */
/* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x03); */
/* pSiS->postVBCR32 &= ~0x03; */
result = sis_do_sense(testsvhs_tempbl, testsvhs_tempbh,
testsvhs_tempcl, testsvhs_tempch);
haveresult = 0;
for (j = 0; j < 10; j++) {
result = 0;
for (i = 0; i < 3; i++) {
if (sis_do_sense(testsvhs_tempbl, testsvhs_tempbh,
testsvhs_tempcl, testsvhs_tempch))
result++;
}
if ((result == 0) || (result >= 2))
break;
}
if (result) {
if (sis_verbose > 1) {
printf
("[SiS] SiS30x: Detected TV connected to SVIDEO output\n");
}
/* TW: So we can be sure that there IS a SVIDEO output */
sis_vbflags |= TV_SVIDEO;
orSISIDXREG(SISCR, 0x32, 0x02);
//pSiS->postVBCR32 |= 0x02;
}
if ((biosflag & 0x02) || (!(result))) {
haveresult = 0;
for (j = 0; j < 10; j++) {
result = 0;
for (i = 0; i < 3; i++) {
if (sis_do_sense(testcvbs_tempbl, testcvbs_tempbh,
testcvbs_tempcl, testcvbs_tempch))
result++;
}
if ((result == 0) || (result >= 2))
break;
}
if (result) {
if (sis_verbose > 1) {
printf
("[SiS] SiS30x: Detected TV connected to COMPOSITE output\n");
}
sis_vbflags |= TV_AVIDEO;
orSISIDXREG(SISCR, 0x32, 0x01);
//pSiS->postVBCR32 |= 0x01;
}
}
sis_do_sense(0, 0, 0, 0);
outSISIDXREG(SISPART2, 0x00, backupP2_00);
outSISIDXREG(SISPART4, 0x0d, backupP4_0d);
}
static void sis_detect_crt1()
{
unsigned char CR32;
unsigned char CRT1Detected = 0;
unsigned char OtherDevices = 0;
if (!(sis_vbflags & VB_VIDEOBRIDGE)) {
sis_crt1_off = 0;
return;
}
inSISIDXREG(SISCR, 0x32, CR32);
if (CR32 & 0x20)
CRT1Detected = 1;
if (CR32 & 0x5F)
OtherDevices = 1;
if (sis_crt1_off == -1) {
if (!CRT1Detected) {
/* BIOS detected no CRT1. */
/* If other devices exist, switch it off */
if (OtherDevices)
sis_crt1_off = 1;
else
sis_crt1_off = 0;
} else {
/* BIOS detected CRT1, leave/switch it on */
sis_crt1_off = 0;
}
}
if (sis_verbose > 0) {
printf("[SiS] %sCRT1 connection detected\n",
sis_crt1_off ? "No " : "");
}
}
#if 0 /* not used yet */
static void sis_detect_lcd()
{
unsigned char CR32;
#if 0
/* not supported yet? */
unsigned char CR36, CR37;
#endif
if (!(sis_vbflags & VB_VIDEOBRIDGE)) {
return;
}
inSISIDXREG(SISCR, 0x32, CR32);
if (CR32 & 0x08)
sis_vbflags |= CRT2_LCD;
/* DDC detection of LCD - not supported yet */
/* Get other misc info about LCD - not supported */
}
#endif
static void sis_detect_tv()
{
unsigned char SR16, SR38, CR32, CR38 = 0, CR79;
int temp = 0;
if (!(sis_vbflags & VB_VIDEOBRIDGE))
return;
inSISIDXREG(SISCR, 0x32, CR32);
inSISIDXREG(SISSR, 0x16, SR16);
inSISIDXREG(SISSR, 0x38, SR38);
switch (sis_vga_engine) {
case SIS_300_VGA:
if (sis_device_id == DEVICE_SIS_630_VGA)
temp = 0x35;
break;
case SIS_315_VGA:
temp = 0x38;
break;
}
if (temp) {
inSISIDXREG(SISCR, temp, CR38);
}
if (CR32 & 0x47)
sis_vbflags |= CRT2_TV;
if (CR32 & 0x04)
sis_vbflags |= TV_SCART;
else if (CR32 & 0x02)
sis_vbflags |= TV_SVIDEO;
else if (CR32 & 0x01)
sis_vbflags |= TV_AVIDEO;
else if (CR32 & 0x40)
sis_vbflags |= (TV_SVIDEO | TV_HIVISION);
else if ((CR38 & 0x04) && (sis_vbflags & (VB_301LV | VB_302LV)))
sis_vbflags |= TV_HIVISION_LV;
else if ((CR38 & 0x04) && (sis_vbflags & VB_CHRONTEL))
sis_vbflags |= (TV_CHSCART | TV_PAL);
else if ((CR38 & 0x08) && (sis_vbflags & VB_CHRONTEL))
sis_vbflags |= (TV_CHHDTV | TV_NTSC);
if (sis_vbflags & (TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION)) {
if (sis_vga_engine == SIS_300_VGA) {
/* TW: Should be SR38 here as well, but this
* does not work. Looks like a BIOS bug (2.04.5c).
*/
if (SR16 & 0x20)
sis_vbflags |= TV_PAL;
else
sis_vbflags |= TV_NTSC;
} else if ((sis_device_id == DEVICE_SIS_550_VGA)) {
inSISIDXREG(SISCR, 0x79, CR79);
if (CR79 & 0x08) {
inSISIDXREG(SISCR, 0x79, CR79);
CR79 >>= 5;
}
if (CR79 & 0x01) {
sis_vbflags |= TV_PAL;
if (CR38 & 0x40)
sis_vbflags |= TV_PALM;
else if (CR38 & 0x80)
sis_vbflags |= TV_PALN;
} else
sis_vbflags |= TV_NTSC;
} else if ((sis_device_id == DEVICE_SIS_650_VGA)) {
inSISIDXREG(SISCR, 0x79, CR79);
if (CR79 & 0x20) {
sis_vbflags |= TV_PAL;
if (CR38 & 0x40)
sis_vbflags |= TV_PALM;
else if (CR38 & 0x80)
sis_vbflags |= TV_PALN;
} else
sis_vbflags |= TV_NTSC;
} else { /* 315, 330 */
if (SR38 & 0x01) {
sis_vbflags |= TV_PAL;
if (CR38 & 0x40)
sis_vbflags |= TV_PALM;
else if (CR38 & 0x80)
sis_vbflags |= TV_PALN;
} else
sis_vbflags |= TV_NTSC;
}
}
if (sis_vbflags &
(TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION | TV_CHSCART |
TV_CHHDTV)) {
if (sis_verbose > 0) {
printf("[SiS] %sTV standard %s\n",
(sis_vbflags & (TV_CHSCART | TV_CHHDTV)) ? "Using " :
"Detected default ",
(sis_vbflags & TV_NTSC) ? ((sis_vbflags & TV_CHHDTV) ?
"480i HDTV" : "NTSC")
: ((sis_vbflags & TV_PALM) ? "PALM"
: ((sis_vbflags & TV_PALN) ? "PALN" : "PAL")));
}
}
}
static void sis_detect_crt2()
{
unsigned char CR32;
if (!(sis_vbflags & VB_VIDEOBRIDGE))
return;
/* CRT2-VGA not supported on LVDS and 30xLV */
if (sis_vbflags & (VB_LVDS | VB_301LV | VB_302LV))
return;
inSISIDXREG(SISCR, 0x32, CR32);
if (CR32 & 0x10)
sis_vbflags |= CRT2_VGA;
#if 0
if (!(pSiS->nocrt2ddcdetection)) {
if (sis_vbflags & (VB_301B | VB_302B)) {
if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD))) {
printf
("[SiS] BIOS detected no secondary VGA, sensing via DDC\n");
if (SiS_SenseVGA2DDC(pSiS->SiS_Pr, pSiS)) {
printf
("[SiS] DDC error during secondary VGA detection\n");
} else {
inSISIDXREG(SISCR, 0x32, CR32);
if (CR32 & 0x10) {
sis_vbflags |= CRT2_VGA;
/*pSiS->postVBCR32 |= 0x10; */
printf
("[SiS] Detected secondary VGA connection\n");
} else {
printf
("[SiS] No secondary VGA connection detected\n");
}
}
}
}
}
#endif
}
/* Preinit: detect video bridge and sense connected devs */
static void sis_detect_video_bridge()
{
int temp, temp1, temp2;
sis_vbflags = 0;
if (sis_vga_engine != SIS_300_VGA && sis_vga_engine != SIS_315_VGA)
return;
inSISIDXREG(SISPART4, 0x00, temp);
temp &= 0x0F;
if (temp == 1) {
inSISIDXREG(SISPART4, 0x01, temp1);
temp1 &= 0xff;
if (temp1 >= 0xE0) {
sis_vbflags |= VB_302LV;
//pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV;
if (sis_verbose > 1) {
printf
("[SiS] Detected SiS302LV video bridge (ID 1; Revision 0x%x)\n",
temp1);
}
} else if (temp1 >= 0xD0) {
sis_vbflags |= VB_301LV;
//pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV;
if (sis_verbose > 1) {
printf
("[SiS] Detected SiS301LV video bridge (ID 1; Revision 0x%x)\n",
temp1);
}
} else if (temp1 >= 0xB0) {
sis_vbflags |= VB_301B;
//pSiS->sishw_ext.ujVBChipID = VB_CHIP_301B;
inSISIDXREG(SISPART4, 0x23, temp2);
if (!(temp2 & 0x02))
sis_vbflags |= VB_30xBDH;
if (sis_verbose > 1) {
printf
("[SiS] Detected SiS301B%s video bridge (Revision 0x%x)\n",
(temp2 & 0x02) ? "" : " (DH)", temp1);
}
} else {
sis_vbflags |= VB_301;
//pSiS->sishw_ext.ujVBChipID = VB_CHIP_301;
if (sis_verbose > 1) {
printf
("[SiS] Detected SiS301 video bridge (Revision 0x%x)\n",
temp1);
}
}
sis_sense_30x();
} else if (temp == 2) {
inSISIDXREG(SISPART4, 0x01, temp1);
temp1 &= 0xff;
if (temp1 >= 0xE0) {
sis_vbflags |= VB_302LV;
//pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV;
if (sis_verbose > 1) {
printf
("[SiS] Detected SiS302LV video bridge (ID 2; Revision 0x%x)\n",
temp1);
}
} else if (temp1 >= 0xD0) {
sis_vbflags |= VB_301LV;
//pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV;
if (sis_verbose > 1) {
printf
("[SiS] Detected SiS301LV video bridge (ID 2; Revision 0x%x)\n",
temp1);
}
} else {
sis_vbflags |= VB_302B;
//pSiS->sishw_ext.ujVBChipID = VB_CHIP_302B;
inSISIDXREG(SISPART4, 0x23, temp2);
if (!(temp & 0x02))
sis_vbflags |= VB_30xBDH;
if (sis_verbose > 1) {
printf
("[SiS] Detected SiS302B%s video bridge (Revision 0x%x)\n",
(temp2 & 0x02) ? "" : " (DH)", temp1);
}
}
sis_sense_30x();
} else if (temp == 3) {
if (sis_verbose > 1) {
printf("[SiS] Detected SiS303 video bridge - not supported\n");
}
} else {
/* big scary mess of code to handle unknown or Chrontel LVDS */
/* skipping it for now */
if (sis_verbose > 1) {
printf
("[SiS] Detected Chrontel video bridge - not supported\n");
}
}
/* this is probably not relevant to video overlay driver... */
/* detects if brdige uses LCDA for low res text modes */
if (sis_vga_engine == SIS_315_VGA) {
if (sis_vbflags & (VB_302B | VB_301LV | VB_302LV)) {
#if 0
if (pSiS->sisfblcda != 0xff) {
if ((pSiS->sisfblcda & 0x03) == 0x03) {
//pSiS->SiS_Pr->SiS_UseLCDA = TRUE;
sis_vbflags |= VB_USELCDA;
}
} else
#endif
{
inSISIDXREG(SISCR, 0x34, temp);
if (temp <= 0x13) {
inSISIDXREG(SISCR, 0x38, temp);
if ((temp & 0x03) == 0x03) {
//pSiS->SiS_Pr->SiS_UseLCDA = TRUE;
sis_vbflags |= VB_USELCDA;
} else {
inSISIDXREG(SISCR, 0x30, temp);
if (temp & 0x20) {
inSISIDXREG(SISPART1, 0x13, temp);
if (temp & 0x40) {
//pSiS->SiS_Pr->SiS_UseLCDA = TRUE;
sis_vbflags |= VB_USELCDA;
}
}
}
}
}
if (sis_vbflags & VB_USELCDA) {
/* printf("Bridge uses LCDA for low resolution and text modes\n"); */
}
}
}
}
/* detect video bridge type and sense connected devices */
void sis_init_video_bridge()
{
sis_detect_video_bridge();
sis_detect_crt1();
//sis_detect_lcd(); /* not fully ready probably */
sis_detect_tv();
sis_detect_crt2();
sis_detected_crt2_devices =
sis_vbflags & (CRT2_LCD | CRT2_TV | CRT2_VGA);
// force crt2 type
if (sis_force_crt2_type == CRT2_DEFAULT) {
if (sis_vbflags & CRT2_VGA)
sis_force_crt2_type = CRT2_VGA;
else if (sis_vbflags & CRT2_LCD)
sis_force_crt2_type = CRT2_LCD;
else if (sis_vbflags & CRT2_TV)
sis_force_crt2_type = CRT2_TV;
}
switch (sis_force_crt2_type) {
case CRT2_TV:
sis_vbflags = sis_vbflags & ~(CRT2_LCD | CRT2_VGA);
if (sis_vbflags & VB_VIDEOBRIDGE)
sis_vbflags = sis_vbflags | CRT2_TV;
else
sis_vbflags = sis_vbflags & ~(CRT2_TV);
break;
case CRT2_LCD:
sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_VGA);
if ((sis_vbflags & VB_VIDEOBRIDGE) /* XXX: && (pSiS->VBLCDFlags) */
)
sis_vbflags = sis_vbflags | CRT2_LCD;
else {
sis_vbflags = sis_vbflags & ~(CRT2_LCD);
if (sis_verbose > 0) {
printf
("[SiS] Can't force CRT2 to LCD, no panel detected\n");
}
}
break;
case CRT2_VGA:
if (sis_vbflags & VB_LVDS) {
if (sis_verbose > 0) {
printf("[SiS] LVDS does not support secondary VGA\n");
}
break;
}
if (sis_vbflags & (VB_301LV | VB_302LV)) {
if (sis_verbose > 0) {
printf
("[SiS] SiS30xLV bridge does not support secondary VGA\n");
}
break;
}
sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_LCD);
if (sis_vbflags & VB_VIDEOBRIDGE)
sis_vbflags = sis_vbflags | CRT2_VGA;
else
sis_vbflags = sis_vbflags & ~(CRT2_VGA);
break;
default:
sis_vbflags &= ~(CRT2_TV | CRT2_LCD | CRT2_VGA);
}
/* CRT2 gamma correction?? */
/* other force modes: */
/* have a 'force tv type' (svideo, composite, scart) option? */
/* have a 'force crt1 type' (to turn it off, etc??) */
/* TW: Check if CRT1 used (or needed; this eg. if no CRT2 detected) */
if (sis_vbflags & VB_VIDEOBRIDGE) {
/* TW: No CRT2 output? Then we NEED CRT1!
* We also need CRT1 if depth = 8 and bridge=LVDS|630+301B
*/
if ((!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV))) || ( /*(pScrn->bitsPerPixel == 8) && */
((sis_vbflags & (VB_LVDS | VB_CHRONTEL)) || ((sis_vga_engine == SIS_300_VGA) && (sis_vbflags & VB_301B))))) {
sis_crt1_off = 0;
}
/* TW: No CRT2 output? Then we can't use hw overlay on CRT2 */
if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV)))
sis_overlay_on_crt1 = 1;
} else { /* TW: no video bridge? */
/* Then we NEED CRT1... */
sis_crt1_off = 0;
/* ... and can't use CRT2 for overlay output */
sis_overlay_on_crt1 = 1;
}
/* tvstandard options ? */
// determine using CRT1 or CRT2?
/* -> NO dualhead right now... */
if (sis_vbflags & DISPTYPE_DISP2) {
if (sis_crt1_off) {
sis_vbflags |= VB_DISPMODE_SINGLE;
/* TW: No CRT1? Then we use the video overlay on CRT2 */
sis_overlay_on_crt1 = 0;
} else /* TW: CRT1 and CRT2 - mirror or dual head ----- */
sis_vbflags |= (VB_DISPMODE_MIRROR | DISPTYPE_CRT1);
} else { /* TW: CRT1 only ------------------------------- */
sis_vbflags |= (VB_DISPMODE_SINGLE | DISPTYPE_CRT1);
}
if (sis_verbose > 0) {
printf("[SiS] Using hardware overlay on CRT%d\n",
sis_overlay_on_crt1 ? 1 : 2);
}
}
--- NEW FILE: mach64.h ---
/*
* mach64.h
* This software has been released under the terms of the GNU Public
* license. See http://www.gnu.org/copyleft/gpl.html for details.
*
* It's based on radeonfb, X11, GATOS sources
*/
#ifndef __MACH64_INCLUDED
#define __MACH64_INCLUDED 1
/* Note: this model of accessing to IO space is based on MMIO technology.
This means that this sources don't support ISA and VLB cards */
#define BlockIOTag(val) (val)
#define IOPortTag(sparce,val) (val)
/* MDA/[M]CGA/EGA/VGA I/O ports */
#define GENVS 0x0102u /* Write (and Read on uC only) */
[...2572 lines suppressed...]
#define MIX_NOT_SRC_AND_DST 0x000eu
#define MIX_NOR 0x000fu
#define MIX_MIN 0x0010u
#define MIX_DST_MINUS_SRC 0x0011u
#define MIX_SRC_MINUS_DST 0x0012u
#define MIX_PLUS 0x0013u
#define MIX_MAX 0x0014u
#define MIX_HALF__DST_MINUS_SRC 0x0015u
#define MIX_HALF__SRC_MINUS_DST 0x0016u
#define MIX_AVERAGE 0x0017u
#define MIX_DST_MINUS_SRC_SAT 0x0018u
#define MIX_SRC_MINUS_DST_SAT 0x001au
#define MIX_HALF__DST_MINUS_SRC_SAT 0x001cu
#define MIX_HALF__SRC_MINUS_DST_SAT 0x001eu
#define MIX_AVERAGE_SAT 0x001fu
#define MIX_FN_PAINT MIX_SRC
#endif
--- NEW FILE: sis_defs.h ---
/**
SiS graphics misc definitions.
Taken from SiS Xv driver:
Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
**/
#ifndef VIDIX_SIS_DEFS_H
#define VIDIX_SIS_DEFS_H
/** PCI IDs **/
#define VENDOR_SIS 0x1039
#define DEVICE_SIS_300 0x0300
#define DEVICE_SIS_315H 0x0310
#define DEVICE_SIS_315 0x0315
#define DEVICE_SIS_315PRO 0x0325
#define DEVICE_SIS_330 0x0330
#define DEVICE_SIS_540 0x0540
#define DEVICE_SIS_540_VGA 0x5300
#define DEVICE_SIS_550 0x0550
#define DEVICE_SIS_550_VGA 0x5315
#define DEVICE_SIS_630 0x0630
#define DEVICE_SIS_630_VGA 0x6300
#define DEVICE_SIS_650 0x0650
#define DEVICE_SIS_650_VGA 0x6325
#define DEVICE_SIS_730 0x0730
/* TW: VBFlags */
#define CRT2_DEFAULT 0x00000001
#define CRT2_LCD 0x00000002 /* TW: Never change the order of the CRT2_XXX entries */
#define CRT2_TV 0x00000004 /* (see SISCycleCRT2Type()) */
#define CRT2_VGA 0x00000008
#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA)
#define DISPTYPE_DISP2 CRT2_ENABLE
#define TV_NTSC 0x00000010
#define TV_PAL 0x00000020
#define TV_HIVISION 0x00000040
#define TV_HIVISION_LV 0x00000080
#define TV_TYPE (TV_NTSC | TV_PAL | TV_HIVISION | TV_HIVISION_LV)
#define TV_AVIDEO 0x00000100
#define TV_SVIDEO 0x00000200
#define TV_SCART 0x00000400
#define TV_INTERFACE (TV_AVIDEO | TV_SVIDEO | TV_SCART | TV_CHSCART | TV_CHHDTV)
#define VB_USELCDA 0x00000800
#define TV_PALM 0x00001000
#define TV_PALN 0x00002000
#define TV_CHSCART 0x00008000
#define TV_CHHDTV 0x00010000
#define VGA2_CONNECTED 0x00040000
#define DISPTYPE_CRT1 0x00080000 /* TW: CRT1 connected and used */
#define DISPTYPE_DISP1 DISPTYPE_CRT1
#define VB_301 0x00100000 /* Video bridge type */
#define VB_301B 0x00200000
#define VB_302B 0x00400000
#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */
#define VB_LVDS 0x01000000
#define VB_CHRONTEL 0x02000000
#define VB_301LV 0x04000000
#define VB_302LV 0x08000000
#define VB_30xLV VB_301LV
#define VB_30xLVX VB_302LV
#define VB_TRUMPION 0x10000000
#define VB_VIDEOBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV| \
VB_LVDS|VB_CHRONTEL|VB_TRUMPION) /* TW */
#define VB_SISBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV)
#define SINGLE_MODE 0x20000000 /* TW: CRT1 or CRT2; determined by DISPTYPE_CRTx */
#define VB_DISPMODE_SINGLE SINGLE_MODE /* TW: alias */
#define MIRROR_MODE 0x40000000 /* TW: CRT1 + CRT2 identical (mirror mode) */
#define VB_DISPMODE_MIRROR MIRROR_MODE /* TW: alias */
#define DUALVIEW_MODE 0x80000000 /* TW: CRT1 + CRT2 independent (dual head mode) */
#define VB_DISPMODE_DUAL DUALVIEW_MODE /* TW: alias */
#define DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE) /* TW */
/* SiS vga engine type */
#define UNKNOWN_VGA 0
#define SIS_300_VGA 1
#define SIS_315_VGA 2
extern unsigned int sis_verbose;
extern unsigned short sis_iobase;
extern unsigned int sis_vga_engine;
extern unsigned int sis_vbflags;
extern unsigned int sis_overlay_on_crt1;
extern unsigned int sis_crt1_off;
extern unsigned int sis_detected_crt2_devices;
extern unsigned int sis_force_crt2_type;
extern unsigned int sis_device_id;
#endif /* VIDIX_SIS_DEFS_H */
--- NEW FILE: nvidia_vid.c ---
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <inttypes.h>
#include "vidix.h"
#include "fourcc.h"
#include "libdha/libdha.h"
#include "libdha/pci_ids.h"
#include "libdha/pci_names.h"
#include "nvidia.h"
#define VIDIX_STATIC nvidia_
static void *ctrl_base = 0;
static void *fb_base = 0;
//static int32_t overlay_offset = 0;
static uint32_t ram_size = 0;
static unsigned int *PFB;
static unsigned int *PCIO;
static unsigned int *PGRAPH;
static unsigned int *PRAMIN;
static unsigned int *FIFO;
static unsigned int *PMC;
typedef unsigned char U008;
#define NVIDIA_MSG "[nvidia-unworking-driver] "
#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
unsigned int nv_fifo_space = 0;
void CRTCout(unsigned char index, unsigned char val)
{
NV_WR08(PCIO, 0x3d4, index);
NV_WR08(PCIO, 0x3d5, val);
}
volatile RivaScaledImage *ScaledImage;
#define CARD_FLAGS_NONE 0x00
#define CARD_FLAGS_NOTSUPPORTED 0x01
struct nv_card_id_s
{
const unsigned int id ;
const char name[32];
const int core;
const int flags;
};
static struct nv_card_id_s nv_card_id;
static const struct nv_card_id_s nv_card_ids[]=
{
{ DEVICE_NVIDIA_NV5_RIVA_TNT2, "nVidia TNT2 (NV5) ", 5, CARD_FLAGS_NOTSUPPORTED},
{ DEVICE_NVIDIA_NV6_VANTA, "nVidia Vanta (NV6.1)", 6, CARD_FLAGS_NOTSUPPORTED},
{ DEVICE_NVIDIA_RIVA_TNT2_MODEL, "nVidia Vanta (NV6.2)", 6, CARD_FLAGS_NOTSUPPORTED}
};
static int find_chip(unsigned int chip_id)
{
unsigned int i;
for (i = 0; i < sizeof(nv_card_ids)/sizeof(struct nv_card_id_s); i++)
if (chip_id == nv_card_ids[i].id)
return(i);
return(-1);
}
static pciinfo_t pci_info;
static int probed = 0;
/* VIDIX exports */
static vidix_capability_t nvidia_cap =
{
"NVIDIA driver for VIDIX",
"alex",
TYPE_OUTPUT,
{ 0, 0, 0, 0 },
2046,
2047,
4,
4,
-1,
FLAG_NONE,
VENDOR_NVIDIA,
0,
{ 0, 0, 0, 0 }
};
unsigned int VIDIX_NAME(vixGetVersion)(void)
{
return(VIDIX_VERSION);
}
int VIDIX_NAME(vixProbe)(int verbose,int force)
{
pciinfo_t lst[MAX_PCI_DEVICES];
unsigned int i, num_pci;
int err;
printf(NVIDIA_MSG"probe\n");
err = pci_scan(lst, &num_pci);
if (err)
{
printf(NVIDIA_MSG"Error occured during pci scan: %s\n", strerror(err));
return err;
}
else
{
err = ENXIO;
for (i = 0; i < num_pci; i++)
{
if (lst[i].vendor == VENDOR_NVIDIA)
{
int idx;
idx = find_chip(lst[i].device);
if (idx == -1)
continue;
if (nv_card_ids[idx].flags & CARD_FLAGS_NOTSUPPORTED)
{
printf(NVIDIA_MSG"Found chip: %s, but not supported!\n",
nv_card_ids[idx].name);
continue;
}
else
printf(NVIDIA_MSG"Found chip: %s\n", nv_card_ids[idx].name);
memcpy(&nv_card_id, &nv_card_ids[idx], sizeof(struct nv_card_id_s));
nvidia_cap.device_id = nv_card_ids[idx].id;
err = 0;
memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
probed = 1;
printf(NVIDIA_MSG"bus:card:func = %x:%x:%x\n",
pci_info.bus, pci_info.card, pci_info.func);
printf(NVIDIA_MSG"vendor:device = %x:%x\n",
pci_info.vendor, pci_info.device);
printf(NVIDIA_MSG"base0:base1:base2:baserom = %lx:%lx:%lx:%lx\n",
pci_info.base0, pci_info.base1, pci_info.base2,
pci_info.baserom);
break;
}
}
}
if (err)
printf(NVIDIA_MSG"No chip found\n");
return(err);
}
int VIDIX_NAME(vixInit)(const char *args)
{
unsigned long card_option;
printf(NVIDIA_MSG"init\n");
pci_config_read(pci_info.bus, pci_info.card, pci_info.func, 0x40,
4, &card_option);
printf(NVIDIA_MSG"card_option: %lx\n", card_option);
if (!probed)
{
printf(NVIDIA_MSG"Driver was not probed but is being initialized\n");
return(EINTR);
}
ctrl_base = map_phys_mem(pci_info.base0, 0x00800000);
if (ctrl_base == (void *)-1)
return(ENOMEM);
fb_base = map_phys_mem(pci_info.base1, 0x01000000);
if (fb_base == (void *)-1)
return(ENOMEM);
printf(NVIDIA_MSG"ctrl_base: %p, fb_base: %p\n", ctrl_base, fb_base);
PFB = ctrl_base+0x00100000;
PGRAPH = ctrl_base+0x00400000;
PRAMIN = ctrl_base+0x00710000;
FIFO = ctrl_base+0x00800000;
PCIO = ctrl_base+0x00601000;
PMC = ctrl_base+0x00000000;
printf(NVIDIA_MSG"pfb: %p, pgraph: %p, pramin: %p, fifo: %p, pcio: %p\n",
PFB, PGRAPH, PRAMIN, FIFO, PCIO);
ScaledImage = FIFO+0x8000/4;
printf(NVIDIA_MSG"ScaledImage: %p\n", ScaledImage);
/* unlock */
CRTCout(0x11, 0xff);
printf(NVIDIA_MSG"fifo_free: %d\n", ScaledImage->fifo_free);
RIVA_FIFO_FREE(ScaledImage, 10);
dump_scaledimage(ScaledImage);
/* create scaled image object */
*(PRAMIN+0x518) = 0x0100A037;
*(PRAMIN+0x519) = 0x00000C02;
/* put scaled image object into subchannel */
*(FIFO+0x2000) = 0x80000011;
/* ram size detection */
switch(nv_card_id.core)
{
case 5:
{
if (*(PFB+0x0) & 0x00000100)
{
printf(NVIDIA_MSG"first ver\n");
ram_size = ((*(PFB+0x0) >> 12) & 0x0f) * 1024 * 2 + 1024 * 2;
}
else
{
printf("second ver (code: %d)\n",
*(PFB+0x0) & 0x00000003);
switch(*(PFB+0x0) & 0x00000003)
{
case 0:
ram_size = 1024*32;
break;
case 1:
ram_size = 1024*4;
break;
case 2:
ram_size = 1024*8;
break;
case 3:
ram_size = 1024*16;
break;
default:
printf(NVIDIA_MSG"Unknown ram size code: %d\n",
*(PFB+0x0) & 0x00000003);
break;
}
}
break;
}
default:
printf(NVIDIA_MSG"Unknown core: %d\n", nv_card_id.core);
}
printf(NVIDIA_MSG"ram_size: %d\n", ram_size);
return 0;
}
void VIDIX_NAME(vixDestroy)(void)
{
printf(NVIDIA_MSG"destory\n");
}
int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to)
{
memcpy(to, &nvidia_cap, sizeof(vidix_capability_t));
return(0);
}
int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to)
{
printf(NVIDIA_MSG"query fourcc (%x)\n", to->fourcc);
to->flags = 0;
to->depth = VID_DEPTH_32BPP;
return 0;
}
int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info)
{
int fb_pixel_size = 32/8;
int fb_line_len = 1280*4;
char buffer = 0;
int offset = 0;
int x,y,h,w;
int bpp = 32 >> 3;
int size;
printf(NVIDIA_MSG"config playback\n");
x = info->src.x;
y = info->src.y;
h = info->src.h;
w = info->src.w;
w = (w + 1) & ~1;
size = h * (((w << 1) + 63) & ~63) / bpp;
PMC[(0x8900/4)+buffer] = offset;
PMC[(0x8928/4)+buffer] = (h << 16) | w;
PMC[(0x8930/4)+buffer] = ((y << 4) & 0xffff0000) | (x >> 12);
PMC[(0x8938/4)+buffer] = (w << 20) / info->dest.w;
PMC[(0x8938/4)+buffer] = (h << 20) / info->dest.h;
info->dga_addr = fb_base + (info->dest.w - info->src.w) * fb_pixel_size /
2 + (info->dest.h - info->src.h) * fb_line_len / 2;
info->num_frames = 1;
info->frame_size = info->src.w*info->src.h+(info->src.w*info->src.h)/2;
info->offsets[0] = 0;
info->offset.y = 0;
info->offset.v = ((info->src.w + 31) & ~31) * info->src.h;
info->offset.u = info->offset.v+((info->src.w + 31) & ~31) * info->src.h / 4;
// info->dga_addr = malloc(info->num_frames*info->frame_size);
return 0;
}
int VIDIX_NAME(vixPlaybackOn)(void)
{
printf(NVIDIA_MSG"playback on\n");
return 0;
}
int VIDIX_NAME(vixPlaybackOff)(void)
{
printf(NVIDIA_MSG"playback off\n");
return 0;
}
--- NEW FILE: pm2_vid.c ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: sis_vid.c ---
/**
VIDIX driver for SiS 300 and 310/325 series chips.
Copyright 2003 Jake Page, Sugar Media.
Based on SiS Xv driver:
Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
[...1523 lines suppressed...]
setvideoreg(Index_VI_Saturation, temp);
}
static void set_hue(uint8_t hue)
{
setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue);
}
#if 0
/* JCP: not used (I don't think it's correct anyway) */
static void set_alpha(uint8_t alpha)
{
uint8_t data;
data = getvideoreg(Index_VI_Key_Overlay_OP);
data &= 0x0F;
setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4));
}
#endif
--- NEW FILE: pm3_regs.h ---
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/pm3_regs.h,v 1.9 2001/11/20 00:09:15 alanh Exp $ */
/*
* glint register file
*
* Copyright by Sven Luther
* Authors: Sven Luther, <luther@dpt-info.u-strasbg.fr>
* Thomas Witzel, <twitzel@nmr.mgh.harvard.edu>
*
* this work is sponsored by Appian Graphics.
*
*/
#ifndef _PM3_REG_H_
#define _PM3_REG_H_
#define PM3FIFOSize 120
#define PM3Tag(r) ((r>>3)&0x7ff)
[...1214 lines suppressed...]
#define RAMDAC_SET_INDEX(index) \
{ \
SLOW_WRITE_REG (PM3RD_IndexHigh,(index>>8)&0xff); \
SLOW_WRITE_REG (PM3RD_IndexLow,index&0xff); \
}
#define RAMDAC_SET_REG(index, data) \
{ \
RAMDAC_SET_INDEX(index); \
SLOW_WRITE_REG(PM3RD_IndexedData, data); \
}
#define RAMDAC_GET_REG(index, temp) \
{ \
RAMDAC_SET_INDEX(index); \
temp = READ_REG(PM3RD_IndexedData); \
}
#endif /* _PM3_REG_H_ */
--- NEW FILE: cyberblade_regs.h ---
/*
* Copyright 1992-2000 by Alan Hourihane, Wigan, England.
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that
* copyright notice and this permission notice appear in supporting
* documentation, and that the name of Alan Hourihane not be used in
* advertising or publicity pertaining to distribution of the software without
* specific, written prior permission. Alan Hourihane makes no representations
* about the suitability of this software for any purpose. It is provided
* "as is" without express or implied warranty.
*
* ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* Author: Alan Hourihane, alanh@fairlite.demon.co.uk
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/trident/trident_regs.h,v 1.22 2002/01/11 13:06:30 alanh Exp $ */
#define DEBUG 1
#define NTSC 14.31818
#define PAL 17.73448
/* General Registers */
#define SPR 0x1F /* Software Programming Register (videoram) */
/* 3C4 */
#define RevisionID 0x09
#define ConfPort1 0x0C
#define ConfPort2 0x0C
#define NewMode2 0x0D
#define OldMode2 0x00 /* Should be 0x0D - dealt with in trident_dac.c */
#define OldMode1 0x0E
#define NewMode1 0x0E
#define Protection 0x11
#define MCLKLow 0x16
#define MCLKHigh 0x17
#define ClockLow 0x18
#define ClockHigh 0x19
#define SSetup 0x20
#define SKey 0x37
#define SPKey 0x57
/* 3x4 */
#define Offset 0x13
#define Underline 0x14
#define CRTCMode 0x17
#define CRTCModuleTest 0x1E
#define FIFOControl 0x20
#define LinearAddReg 0x21
#define DRAMTiming 0x23
#define New32 0x23
#define RAMDACTiming 0x25
#define CRTHiOrd 0x27
#define AddColReg 0x29
#define InterfaceSel 0x2A
#define HorizOverflow 0x2B
#define GETest 0x2D
#define Performance 0x2F
#define GraphEngReg 0x36
#define I2C 0x37
#define PixelBusReg 0x38
#define PCIReg 0x39
#define DRAMControl 0x3A
#define MiscContReg 0x3C
#define CursorXLow 0x40
#define CursorXHigh 0x41
#define CursorYLow 0x42
#define CursorYHigh 0x43
#define CursorLocLow 0x44
#define CursorLocHigh 0x45
#define CursorXOffset 0x46
#define CursorYOffset 0x47
#define CursorFG1 0x48
#define CursorFG2 0x49
#define CursorFG3 0x4A
#define CursorFG4 0x4B
#define CursorBG1 0x4C
#define CursorBG2 0x4D
#define CursorBG3 0x4E
#define CursorBG4 0x4F
#define CursorControl 0x50
#define PCIRetry 0x55
#define PreEndControl 0x56
#define PreEndFetch 0x57
#define PCIMaster 0x60
#define Enhancement0 0x62
#define NewEDO 0x64
/* --- Additions by AMR for Vidix support --- */
#define VideoWin1_HScale 0x80
#define VideoWin1_VScale 0x82
#define VideoWin1_Start 0x86
#define VideoWin1_Stop 0x8a
#define Video_Flags 0x8e
#define VideoWin1_Y_BPR 0x90
#define VideoWin1_Y_Offset 0x92
#define Video_LineBufferThreshold 0x95
#define Video_LineBufferLevel 0x96
#define Video_Flags2 0x97
/* --- */
#define TVinterface 0xC0
#define TVMode 0xC1
#define ClockControl 0xCF
/* 3CE */
#define MiscExtFunc 0x0F
#define MiscIntContReg 0x2F
#define CyberControl 0x30
#define CyberEnhance 0x31
#define FPConfig 0x33
#define VertStretch 0x52
#define HorStretch 0x53
#define BiosMode 0x5c
#define BiosNewMode1 0x5a
#define BiosNewMode2 0x5c
#define BiosReg 0x5d
/* --- IO Macros by AMR --- */
#define CRINB(reg) (OUTPORT8(0x3d4,reg), INPORT8(0x3d5))
#define SRINB(reg) (OUTPORT8(0x3c4,reg), INPORT8(0x3c5))
#define CROUTB(reg,val) (OUTPORT8(0x3d4,reg), OUTPORT8(0x3d5,val))
#define SROUTB(reg,val) (OUTPORT8(0x3c4,reg), OUTPORT8(0x3c5,val))
/* --- */
--- NEW FILE: glint_regs.h ---
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/glint_regs.h,v 1.31 2001/12/08 16:01:52 alanh Exp $ */
/*
* glint register file
*
* Copyright by Stefan Dirsch, Dirk Hohndel, Alan Hourihane
* Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
* Dirk Hohndel, <hohndel@suse.de>
* Stefan Dirsch, <sndirsch@suse.de>
* Simon P., <sim@suse.de>
*
* this work is sponsored by S.u.S.E. GmbH, Fuerth, Elsa GmbH, Aachen and
* Siemens Nixdorf Informationssysteme
*
*/
#ifndef _GLINTREG_H_
#define _GLINTREG_H_
[...1265 lines suppressed...]
#define P2VOUT(address) \
Permedia2vOutIndReg(pScrn, address, 0x00, pReg->DacRegs[address]);
#define P2VIN(address) \
pReg->DacRegs[address] = Permedia2vInIndReg(pScrn, address);
/* RamDac Save/Restore functions, used by external DAC's */
#define STORERAMDAC(address,value) \
ramdacReg->DacRegs[address] = value;
/* Multi Chip access */
#define ACCESSCHIP1() \
pGlint->IOOffset = 0;
#define ACCESSCHIP2() \
pGlint->IOOffset = 0x10000;
#endif
--- NEW FILE: pm3_vid.c ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: cyberblade_vid.c ---
(This appears to be a binary file; contents omitted.)
--- NEW FILE: Makefile.in ---
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# @configure_input@
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
# 2003, 2004 Free Software Foundation, Inc.
# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.
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HAVE_IRIXAL_FALSE = @HAVE_IRIXAL_FALSE@
HAVE_IRIXAL_TRUE = @HAVE_IRIXAL_TRUE@
HAVE_LIBFAME_FALSE = @HAVE_LIBFAME_FALSE@
HAVE_LIBFAME_TRUE = @HAVE_LIBFAME_TRUE@
HAVE_LIBMNG_FALSE = @HAVE_LIBMNG_FALSE@
HAVE_LIBMNG_TRUE = @HAVE_LIBMNG_TRUE@
HAVE_LIBPNG_FALSE = @HAVE_LIBPNG_FALSE@
HAVE_LIBPNG_TRUE = @HAVE_LIBPNG_TRUE@
HAVE_LIBRTE_FALSE = @HAVE_LIBRTE_FALSE@
HAVE_LIBRTE_TRUE = @HAVE_LIBRTE_TRUE@
HAVE_LIBSMBCLIENT_FALSE = @HAVE_LIBSMBCLIENT_FALSE@
HAVE_LIBSMBCLIENT_TRUE = @HAVE_LIBSMBCLIENT_TRUE@
HAVE_LINUX_CDROM = @HAVE_LINUX_CDROM@
HAVE_LINUX_FALSE = @HAVE_LINUX_FALSE@
HAVE_LINUX_TRUE = @HAVE_LINUX_TRUE@
HAVE_MACOSX_VIDEO_FALSE = @HAVE_MACOSX_VIDEO_FALSE@
HAVE_MACOSX_VIDEO_TRUE = @HAVE_MACOSX_VIDEO_TRUE@
HAVE_MLIB_FALSE = @HAVE_MLIB_FALSE@
HAVE_MLIB_TRUE = @HAVE_MLIB_TRUE@
HAVE_OPENGL_FALSE = @HAVE_OPENGL_FALSE@
HAVE_OPENGL_TRUE = @HAVE_OPENGL_TRUE@
HAVE_OSS_FALSE = @HAVE_OSS_FALSE@
HAVE_OSS_TRUE = @HAVE_OSS_TRUE@
HAVE_POLYPAUDIO_FALSE = @HAVE_POLYPAUDIO_FALSE@
HAVE_POLYPAUDIO_TRUE = @HAVE_POLYPAUDIO_TRUE@
HAVE_SDL_FALSE = @HAVE_SDL_FALSE@
HAVE_SDL_TRUE = @HAVE_SDL_TRUE@
HAVE_SGMLTOOLS_FALSE = @HAVE_SGMLTOOLS_FALSE@
HAVE_SGMLTOOLS_TRUE = @HAVE_SGMLTOOLS_TRUE@
HAVE_SOLARIS_CDROM = @HAVE_SOLARIS_CDROM@
HAVE_SPEEX_FALSE = @HAVE_SPEEX_FALSE@
HAVE_SPEEX_TRUE = @HAVE_SPEEX_TRUE@
HAVE_STK_FALSE = @HAVE_STK_FALSE@
HAVE_STK_TRUE = @HAVE_STK_TRUE@
HAVE_SUNAUDIO_FALSE = @HAVE_SUNAUDIO_FALSE@
HAVE_SUNAUDIO_TRUE = @HAVE_SUNAUDIO_TRUE@
HAVE_SUNDGA_FALSE = @HAVE_SUNDGA_FALSE@
HAVE_SUNDGA_TRUE = @HAVE_SUNDGA_TRUE@
HAVE_SUNFB_FALSE = @HAVE_SUNFB_FALSE@
HAVE_SUNFB_TRUE = @HAVE_SUNFB_TRUE@
HAVE_SYNCFB_FALSE = @HAVE_SYNCFB_FALSE@
HAVE_SYNCFB_TRUE = @HAVE_SYNCFB_TRUE@
HAVE_THEORA_FALSE = @HAVE_THEORA_FALSE@
HAVE_THEORA_TRUE = @HAVE_THEORA_TRUE@
HAVE_V4L_FALSE = @HAVE_V4L_FALSE@
HAVE_V4L_TRUE = @HAVE_V4L_TRUE@
HAVE_VCDNAV_FALSE = @HAVE_VCDNAV_FALSE@
HAVE_VCDNAV_TRUE = @HAVE_VCDNAV_TRUE@
HAVE_VIDIX_FALSE = @HAVE_VIDIX_FALSE@
HAVE_VIDIX_TRUE = @HAVE_VIDIX_TRUE@
HAVE_VLDXVMC_FALSE = @HAVE_VLDXVMC_FALSE@
HAVE_VLDXVMC_TRUE = @HAVE_VLDXVMC_TRUE@
HAVE_VORBIS_FALSE = @HAVE_VORBIS_FALSE@
HAVE_VORBIS_TRUE = @HAVE_VORBIS_TRUE@
HAVE_W32DLL_FALSE = @HAVE_W32DLL_FALSE@
HAVE_W32DLL_TRUE = @HAVE_W32DLL_TRUE@
HAVE_WIN32_CDROM = @HAVE_WIN32_CDROM@
HAVE_X11_FALSE = @HAVE_X11_FALSE@
HAVE_X11_TRUE = @HAVE_X11_TRUE@
HAVE_XVMC_FALSE = @HAVE_XVMC_FALSE@
HAVE_XVMC_TRUE = @HAVE_XVMC_TRUE@
HAVE_XV_FALSE = @HAVE_XV_FALSE@
HAVE_XV_TRUE = @HAVE_XV_TRUE@
HAVE_XXMC_FALSE = @HAVE_XXMC_FALSE@
HAVE_XXMC_TRUE = @HAVE_XXMC_TRUE@
HAVE_ZLIB_FALSE = @HAVE_ZLIB_FALSE@
HAVE_ZLIB_TRUE = @HAVE_ZLIB_TRUE@
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HOST_OS_DARWIN_TRUE = @HOST_OS_DARWIN_TRUE@
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KSTAT_LIBS = @KSTAT_LIBS@
LDFLAGS = @LDFLAGS@
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LIBCDIO_LIBS = @LIBCDIO_LIBS@
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LIBFFMPEG_CFLAGS = @LIBFFMPEG_CFLAGS@
LIBFLAC_CFLAGS = @LIBFLAC_CFLAGS@
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LIBISO9660_LIBS = @LIBISO9660_LIBS@
LIBMODPLUG_CFLAGS = @LIBMODPLUG_CFLAGS@
LIBMODPLUG_LIBS = @LIBMODPLUG_LIBS@
LIBMPEG2_CFLAGS = @LIBMPEG2_CFLAGS@
LIBNAME = @LIBNAME@
LIBOBJS = @LIBOBJS@
LIBPNG_CONFIG = @LIBPNG_CONFIG@
LIBS = @LIBS@
LIBSMBCLIENT_LIBS = @LIBSMBCLIENT_LIBS@
LIBSTK_CFLAGS = @LIBSTK_CFLAGS@
LIBSTK_LIBS = @LIBSTK_LIBS@
LIBTOOL = $(SHELL) $(top_builddir)/libtool-nofpic
LIBTOOL_DEPS = @LIBTOOL_DEPS@
LIBVCDINFO_LIBS = @LIBVCDINFO_LIBS@
LIBVCD_CFLAGS = @LIBVCD_CFLAGS@
LIBVCD_LIBS = @LIBVCD_LIBS@
LIBVCD_SYSDEP = @LIBVCD_SYSDEP@
LINUX_CDROM_TIMEOUT = @LINUX_CDROM_TIMEOUT@
LINUX_INCLUDE = @LINUX_INCLUDE@
LN_S = @LN_S@
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LT_AGE = @LT_AGE@
LT_CURRENT = @LT_CURRENT@
LT_REVISION = @LT_REVISION@
MAKEINFO = @MAKEINFO@
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PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
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PATH_SEPARATOR = @PATH_SEPARATOR@
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PNG_LIBS = @PNG_LIBS@
POFILES = @POFILES@
POLYPAUDIO_CFLAGS = @POLYPAUDIO_CFLAGS@
POLYPAUDIO_LIBS = @POLYPAUDIO_LIBS@
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includedir = @includedir@
infodir = @infodir@
install_sh = @install_sh@
libdir = $(XINE_PLUGINDIR)/vidix
libexecdir = @libexecdir@
localstatedir = @localstatedir@
mandir = @mandir@
mkdir_p = @mkdir_p@
oldincludedir = @oldincludedir@
prefix = @prefix@
program_transform_name = @program_transform_name@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
sysconfdir = @sysconfdir@
target = @target@
target_alias = @target_alias@
target_cpu = @target_cpu@
target_os = @target_os@
target_vendor = @target_vendor@
w32_path = @w32_path@
XINE_LIB = $(top_builddir)/src/xine-engine/libxine.la
EXTRA_DIST = genfb_vid.c nvidia_vid.c
@HAVE_VIDIX_TRUE@vidix_drivers = \
@HAVE_VIDIX_TRUE@ mach64_vid.la \
@HAVE_VIDIX_TRUE@ mga_crtc2_vid.la \
@HAVE_VIDIX_TRUE@ mga_vid.la \
@HAVE_VIDIX_TRUE@ pm2_vid.la \
@HAVE_VIDIX_TRUE@ pm3_vid.la \
@HAVE_VIDIX_TRUE@ radeon_vid.la \
@HAVE_VIDIX_TRUE@ rage128_vid.la \
@HAVE_VIDIX_TRUE@ cyberblade_vid.la \
@HAVE_VIDIX_TRUE@ sis_vid.la
lib_LTLIBRARIES = $(vidix_drivers)
radeon_vid_la_SOURCES = radeon_vid.c
radeon_vid_la_LIBADD = -lm
radeon_vid_la_LDFLAGS = -avoid-version -module
rage128_vid_la_SOURCES = rage128_vid.c
rage128_vid_la_LDFLAGS = -avoid-version -module
pm2_vid_la_SOURCES = pm2_vid.c
pm2_vid_la_LDFLAGS = -avoid-version -module
pm3_vid_la_SOURCES = pm3_vid.c
pm3_vid_la_LDFLAGS = -avoid-version -module
mach64_vid_la_SOURCES = mach64_vid.c
mach64_vid_la_LDFLAGS = -avoid-version -module
mga_vid_la_SOURCES = mga_vid.c
mga_vid_la_LIBADD = -lm
mga_vid_la_LDFLAGS = -avoid-version -module
mga_crtc2_vid_la_SOURCES = mga_crtc2_vid.c
mga_crtc2_vid_la_LIBADD = -lm
mga_crtc2_vid_la_LDFLAGS = -avoid-version -module
cyberblade_vid_la_SOURCES = cyberblade_vid.c
cyberblade_vid_la_LDFLAGS = -avoid-version -module
sis_vid_la_SOURCES = sis_vid.c sis_bridge.c
sis_vid_la_LDFLAGS = -avoid-version -module
noinst_HEADERS = mach64.h nvidia.h glint_regs.h pm3_regs.h radeon.h \
cyberblade_regs.h sis_defs.h sis_regs.h
AM_CPPFLAGS = -I$(top_srcdir)/src/video_out/vidix \
-I$(top_srcdir)/src/video_out/libdha \
-I$(top_builddir)/src/video_out/libdha
all: all-am
.SUFFIXES:
.SUFFIXES: .c .lo .o .obj
$(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(top_srcdir)/misc/Makefile.common $(am__configure_deps)
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \
&& exit 0; \
exit 1;; \
esac; \
done; \
echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu src/video_out/vidix/drivers/Makefile'; \
cd $(top_srcdir) && \
$(AUTOMAKE) --gnu src/video_out/vidix/drivers/Makefile
.PRECIOUS: Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \
*config.status*) \
cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
*) \
echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
esac;
$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
$(top_srcdir)/configure: $(am__configure_deps)
cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
$(ACLOCAL_M4): $(am__aclocal_m4_deps)
cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
install-libLTLIBRARIES: $(lib_LTLIBRARIES)
@$(NORMAL_INSTALL)
test -z "$(libdir)" || $(mkdir_p) "$(DESTDIR)$(libdir)"
@list='$(lib_LTLIBRARIES)'; for p in $$list; do \
if test -f $$p; then \
f=$(am__strip_dir) \
echo " $(LIBTOOL) --mode=install $(libLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(libdir)/$$f'"; \
$(LIBTOOL) --mode=install $(libLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(libdir)/$$f"; \
else :; fi; \
done
uninstall-libLTLIBRARIES:
@$(NORMAL_UNINSTALL)
@set -x; list='$(lib_LTLIBRARIES)'; for p in $$list; do \
p=$(am__strip_dir) \
echo " $(LIBTOOL) --mode=uninstall rm -f '$(DESTDIR)$(libdir)/$$p'"; \
$(LIBTOOL) --mode=uninstall rm -f "$(DESTDIR)$(libdir)/$$p"; \
done
clean-libLTLIBRARIES:
-test -z "$(lib_LTLIBRARIES)" || rm -f $(lib_LTLIBRARIES)
@list='$(lib_LTLIBRARIES)'; for p in $$list; do \
dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \
test "$$dir" != "$$p" || dir=.; \
echo "rm -f \"$${dir}/so_locations\""; \
rm -f "$${dir}/so_locations"; \
done
cyberblade_vid.la: $(cyberblade_vid_la_OBJECTS) $(cyberblade_vid_la_DEPENDENCIES)
$(LINK) $(am_cyberblade_vid_la_rpath) $(cyberblade_vid_la_LDFLAGS) $(cyberblade_vid_la_OBJECTS) $(cyberblade_vid_la_LIBADD) $(LIBS)
mach64_vid.la: $(mach64_vid_la_OBJECTS) $(mach64_vid_la_DEPENDENCIES)
$(LINK) $(am_mach64_vid_la_rpath) $(mach64_vid_la_LDFLAGS) $(mach64_vid_la_OBJECTS) $(mach64_vid_la_LIBADD) $(LIBS)
mga_crtc2_vid.la: $(mga_crtc2_vid_la_OBJECTS) $(mga_crtc2_vid_la_DEPENDENCIES)
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# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
--- NEW FILE: radeon_vid.c ---
/*
radeon_vid - VIDIX based video driver for Radeon and Rage128 chips
Copyrights 2002 Nick Kurshev. This file is based on sources from
GATOS (gatos.sf.net) and X11 (www.xfree86.org)
Licence: GPL
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <inttypes.h>
#include <sys/types.h>
#include <sys/mman.h>
#include "bswap.h"
#include "pci_ids.h"
#include "pci_names.h"
#include "vidix.h"
[...3309 lines suppressed...]
{
int retval;
if(mlock(dmai->src,dmai->size) != 0) return errno;
retval = radeon_setup_frame(dmai);
if(retval == 0) retval = radeon_transfer_frame();
munlock(dmai->src,dmai->size);
return retval;
}
int VIDIX_NAME(vixQueryDMAStatus)( void )
{
int bm_active;
#if 1 //def RAGE128
bm_active=(INREG(GEN_INT_STATUS)&0x00010000)==0?1:0;
#else
bm_active=(INREG(GEN_INT_STATUS)&(1<<30))==0?1:0;
#endif
return bm_active?1:0;
}
#endif