[sane-devel] Canon LiDE 90
guillaume.gastebois at free.fr
Fri Feb 22 22:12:23 UTC 2008
> So, we need to check what parts of the clocking we need to setup
> reg sane windows
> 0x1a 0x00 0x24 enable clock 3,4 manual output, invert clock 4
> 0x1d 0x04 0x02 just a smaller toggle "shoulder".
> 0x71 0x00 0x05 RS signal seems to be not used.
> 0x72 0x00 0x07 CP signal seems to be not used.
> 0x73 0x00 0x09 CP signal seems to be not used.
> 0x75 0x00 0x01 clock 1 bitmap
> 0x76 0x00 0xff clock 1 bitmap
> 0x79 0x00 0x3f clock 3 bitmap
> 0x7c 0x00 0x1e clock 4 bitmap
> 0x7d 0x00 0x11 change RS on falling edge of system clock, use DLY
> 0x7f 0x00 0x50 delay each of BSMP and VSMP by 8.33ns (DLY)
> The clock 1 stuff seems to be not needed, as it is in automatic mode.
> But clock 3/4 look interesting. The delay of BSMP/VSMP may be useful, too.
0x1a was still 0x24. I modified 0x1d which was 0x04 to 0x02. Result is
I doesn't find where to modify 0x71-0x7f !!!
>> Another thing : I always have a brither vertical line where there is a
>> small black rectangle in the calibration area.
> The small black rectangle is included when acquiring the white level.
> Reduce shading_lines(second to last entry) in Genesys_Model to 250, that
> way it is not seen anymore.
> Oh, and please update from cvs again. A small mistake in
> gl841_bulk_write_registers made the debug register dumps useless.
Another thing : when I make several scan with sane backend and sane
command line, I have alternatively brite and dark images !!! Why ???
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