[yosys] 09/38: Disabled (unused) Xilinx tristate buffers

[Ruben Undheim]

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rubund-guest pushed a commit to tag upstream/0.5.0
in repository yosys.

commit 853e949c0efcf4607fad6d3d4d138f78e1357253
Author: Clifford Wolf <clifford at clifford.at>
Date:   Wed Feb 4 16:33:59 2015 +0100

    Disabled (unused) Xilinx tristate buffers
---
 techlibs/xilinx/cells_sim.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c7f07e4..1f114a2 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -23,13 +23,13 @@ module BUFG(output O, input I);
   assign O = I;
 endmodule
 
-module OBUFT(output O, input I, T);
-  assign O = T ? 1'bz : I;
-endmodule
+// module OBUFT(output O, input I, T);
+//   assign O = T ? 1'bz : I;
+// endmodule
 
-module IOBUF(inout IO, output O, input I, T);
-  assign O = IO, IO = T ? 1'bz : I;
-endmodule
+// module IOBUF(inout IO, output O, input I, T);
+//   assign O = IO, IO = T ? 1'bz : I;
+// endmodule
 
 module INV(output O, input I);
   assign O = !I;

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