[yosys] branch master updated (0fa23a0 -> 9e6e875)
Sebastian Kuzminsky
seb_kuzminsky-guest at moszumanska.debian.org
Fri Mar 4 05:09:46 UTC 2016
This is an automated email from the git hooks/post-receive script.
seb_kuzminsky-guest pushed a change to branch master
in repository yosys.
from 0fa23a0 Added autopkgtest
adds f422186 Added examples/ top-level directory
adds 3a22b31 Added write_smt2 -wires
adds 2916052 Added smtbmc.py
adds 7bcd2a4 Implemented smtbmc.py -i
adds 821f1b8 Added yosys-smtbmc
adds d7de0f4 Improvements in yosys-smtbmc
adds 3c31572 Added yosys-smtbmc copyright
adds 7d3a3a3 Added first help messages for cell types
adds 87adb52 Added more cell descriptions
adds 25c1f6e Added "prep" command
adds 9fd0f87 Fixed yosys-smtbmc -c
adds 5dd3e93 More "yosys-smtbmc -c" fixes
adds 1d83854 Bugfixes in handling of "keep" attribute on wires
adds 302166d Improvements in yosys-smtbmc
adds 5308c1e Fixed bug in verilog parser
adds 255bb91 Progress in yosys-smtbmc
adds 5d1c0ce Progress on cell help messages
adds bbcbf73 Progress on cell help messages
adds 6416dfe Improved inout handling in equiv_make
adds 00e05b1 Added equiv_struct command
adds 84a07ff Added equiv_purge
adds d19069b Improvements in equiv_struct
adds 15a6739 Also merge $equiv cells in equiv_struct
adds 281a033 Added support for ":" as comment symbol after ;-parsing
adds c35db8c Disabled "Skipping blackbox module" msg in show command
adds 4cec1c0 Added equiv_mark command
adds 2a0f577 Fixed handling of driver-driver conflicts in wreduce
adds 6fe48cf equiv_purge bugfix, using SigChunk in Yosys namespace
adds a1c3df7 Fixed driver conflict handling (various cmds)
adds 6af8076 improvement in "stat"
adds 7f110e7 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
adds 453736d Improvements in equiv_struct
adds 83bd27b equiv_struct now creates equiv_merged attributes
adds da923c1 Added "equiv_add -cell"
adds 207736b Import more std:: stuff into Yosys namespace
adds d014ba2 Major refactoring of equiv_struct
adds 27714ac Improvements in equiv_struct
adds 09b4050 Added hashlib::mfp and new SigMap
adds f3db70d Removed old SigMap implementation
adds 0c202a2 Use mfp<> in equiv_mark
adds e69efec Improvements in new SigMap
adds 1e32e4b Improved SigMap performance
adds 8648089 Bugfix in Xilinx LUT mapping
adds ccdbf41 Improvements in wreduce
adds ddf3e2d Bugfix in memory_dff
adds f401eeb Bugfix in mapping $tribuf to $_TBUF_
adds 3ad7420 Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
adds 1ec6429 Added "singleton" pass
adds 8c2bdef Fix a segfault in dffinit when the value has too few bits
adds faa3da5 Merge pull request #97 from zeldin/master
adds d98d99a Added "abc -g"
adds 34f2b84 Fixed handling of parameters and localparams in functions
adds 7ae3d1b More bugfixes in handling of parameters in tasks and functions
adds fd3e10c Link to vlsitechnology.org for liberty files
adds b18f3a2 Changes for Verific 3.16_484_32_151112
adds 415e0a1 Fixed performance bug in Verific importer
adds e61c7f8 Added torder command
adds c86fbae Fixed handling of re-declarations of wires in tasks and functions
adds 8ff229a Fixed WE/RE usage in iCE40 BRAM mapping
adds 0793f1b Added ice40_ffinit pass
adds 6459e3a Removed dangling ';' in rtlil.h
adds ab2d8e5 Added PRIM_DLATCHRS support to verific front-end
adds a7ffb85 Merge branch 'master' of github.com:cliffordwolf/yosys
adds 32f5ee1 Fixed performance bug in ilang parser
adds 4a697ac Fixed oom bug in ilang parser
adds 0f94902 Added tests/simple/graphtest.v
adds 276101f Re-added SigMap::allbits()
adds 33a5b28 Added default values for hashlib at() methods
adds 1ea6db3 Improved proc_mux performance for huge always blocks
adds 9f5b6e4 Added LO to ICESTORM_LC for LUT cascade route.
adds 4d0a6da Merge pull request #108 from cseed/master
adds 494e5f2 Added "synth_ice40 -abc2"
adds 93f6f68 Remove nonportable "-r" option from xargs
adds 7948156 Mac build fix, gsed -> sed
adds 9df59f0 Merge pull request #110 from scanlime/master
adds 47fac57 Added yosys-smtbmc -S
adds 5e90a78 Various improvements in BLIF front-end
adds ab0c44d Added %R select expression
adds f1b959d Run opt_const before check in default scripts
adds ec93d25 Improved ice40_ffinit
adds 8bf452c Bugfix in ice40_ffinit
adds 3102ffb Improvements in ice40_opt
adds 2ee6082 Re-run ice40_opt in "synth_ice40 -abc2"
adds 1d62f87 Fixed "splitnets -ports" for hierarchical designs
adds 1f8c47f Added "equiv_add -try" mode
adds c3fd03d Added "equiv_struct -maxiter <N>"
adds 4393a8f Added "write_blif -cname" mode
adds d00c63c Added "submod -copy"
adds f5008f4 Bugfixes in equiv_struct
adds 8b3f8cd Added "equiv_struct -fwonly"
adds fe97110 Addedd clang sanitizers
adds 9e26147 rtlil: change IdString comparison operators to take references instead of copies
adds 12ebdef rtlil: duplicate remove2() for std::set<>
adds 4375655 rtlil: rewrite remove2() to avoid copying
adds aed8fb3 Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys
adds 5462399 Meaningless coding style change
adds 71f418c More clang sanitizer stuff
adds cd3e109 rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
adds 34969d4 genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
adds 89dc40f rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
adds 0265d7b rtlil: speed up SigSpec::sort_and_unify()
adds 3c48de8 rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)
adds 173fc4f Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys
adds 13e15a2 Added reserve() method to haslib classes and calculate hashtable size based on entries capacity, not size
adds ea492ab hashlib mfp<> performance improvements
adds 01bcc56 SigMap performance improvement
adds 9251553 Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)
adds 17372d8 Added "abc -luts" option, Improved Xilinx logic mapping
adds bd10927 Progress in cell library documentation
adds 7ef613e Updated ABC to hg rev ee212a9e94df
adds 74657f8 Added CodeOfConduct
adds d6592d5 Use alphanumerical order instead of idstring idx in opt_clean compare_signals()
adds ba407da Added addBufGate module method
adds d69395c Added dffsr2dff
adds 801c022 Improved dffsr2dff pass
adds 4a3e1de Updated verific build instructions
adds 6a27cbe Bugfix in Verific front-end
adds 825b99e Added "stat -liberty" for calculating chip area
adds e7bec9b Updated ABC
adds 0ccfb88 Work around DDR dout sim glitches in ice40 SB_IO sim model
adds 840a6dc Updated ABC
adds 7bd329a Support for more Verific primitives (patch I got per email)
adds a75f94e Run dffsr2dff in synth_xilinx
adds 0d7fd25 Added "int ceil_log2(int)" function
adds 0373bd9 Fixed MXE ABC build
adds 6f1d694 Merge branch 'master' of github.com:cliffordwolf/yosys
adds bcc873b Fixed some visual studio warnings
adds 0c4b311 Fixed more visual studio warnings
adds 0761ad6 Changelog for upcoming 0.6 release
adds 85fe6d1 Updated command reference in manual
adds 7a9257e Updated ABC to ae7d65e71adc
adds 45af4a4 Use easyer-to-read unoptimized ceil_log2()
adds 22c549a Fixed BLIF parser for empty port assignments
adds 5869d26 Yosys 0.6
new 93b1bcd Merge tag 'upstream/0.6' into new
new 62e3008 update changelog for 0.6-1
new b34624a refresh gitrevision patch
new 4d50d04 fix upstream spelling mistakes
new b324a60 don't run "make" as part of override_dh_auto_configure
new 85acb59 enable parallel compilation
new d280e48 add a manpage for yosys-smtbmc
new 25ea55c handle yosys-smtbmc's dependency on python
new 788e45a d/control: add Seb to the uploaders
new 9e6e875 dch: switch from UNRELEASED to unstable
The 10 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
.gitignore | 1 +
CHANGELOG | 88 +++
CodeOfConduct | 73 ++
CodingReadme | 7 +-
Makefile | 44 +-
README | 12 +-
backends/blif/blif.cc | 13 +-
backends/btor/btor.cc | 16 +-
backends/smt2/Makefile.inc | 13 +
backends/smt2/example.v | 11 +
backends/smt2/example.ys | 3 +
backends/smt2/smt2.cc | 31 +-
backends/smt2/smtbmc.py | 225 ++++++
backends/smt2/smtio.py | 325 +++++++++
backends/smv/smv.cc | 10 +-
debian/changelog | 17 +
debian/control | 5 +-
debian/man/.gitignore | 1 +
debian/man/genmanpages.sh | 3 +
debian/man/yosys-smtbmc.txt | 44 ++
debian/patches/01_gitrevision.patch | 12 +-
debian/patches/series | 1 +
debian/patches/spelling-fixes.patch | 55 ++
debian/rules | 14 +-
debian/yosys.manpages | 1 +
.../example_basys3 => examples/basys3}/README | 3 +
.../example_basys3 => examples/basys3}/example.v | 0
.../example_basys3 => examples/basys3}/example.xdc | 0
.../example_basys3 => examples/basys3}/run.sh | 0
.../basys3}/run_prog.tcl | 0
.../basys3}/run_vivado.tcl | 0
.../basys3}/run_yosys.ys | 0
{techlibs => examples}/cmos/cmos_cells.lib | 0
{techlibs => examples}/cmos/cmos_cells.sp | 0
{techlibs => examples}/cmos/cmos_cells.v | 0
{techlibs => examples}/cmos/counter.v | 0
{techlibs => examples}/cmos/counter.ys | 0
{techlibs => examples}/cmos/testbench.sh | 0
{techlibs => examples}/cmos/testbench.sp | 0
misc/example.cc => examples/cxx-api/demomain.cc | 2 +-
frontends/ast/ast.cc | 2 +-
frontends/ast/genrtlil.cc | 53 +-
frontends/ast/simplify.cc | 77 +-
frontends/blif/blifparse.cc | 127 ++--
frontends/blif/blifparse.h | 2 +-
frontends/ilang/ilang_parser.y | 24 +-
frontends/verific/Makefile.inc | 5 +-
frontends/verific/build_amd64.txt | 2 -
frontends/verific/verific.cc | 84 ++-
frontends/verilog/verilog_parser.y | 4 +-
kernel/calc.cc | 20 +-
kernel/cellaigs.cc | 2 +-
kernel/driver.cc | 2 +-
kernel/hashlib.h | 149 +++-
kernel/macc.h | 4 +-
kernel/modtools.h | 27 +-
kernel/register.cc | 51 +-
kernel/rtlil.cc | 213 ++++--
kernel/rtlil.h | 16 +-
kernel/satgen.h | 2 +-
kernel/sigtools.h | 166 +----
kernel/yosys.cc | 14 +-
kernel/yosys.h | 11 +
libs/ezsat/ezsat.cc | 24 +-
manual/CHAPTER_Appnotes.tex | 4 +
manual/clean.sh | 2 +-
manual/command-reference-manual.tex | 374 +++++++++-
passes/cmds/Makefile.inc | 1 +
passes/cmds/edgetypes.cc | 6 +-
passes/cmds/plugin.cc | 2 +-
passes/cmds/qwp.cc | 20 +-
passes/cmds/scc.cc | 4 +-
passes/cmds/select.cc | 50 ++
passes/cmds/show.cc | 2 +-
passes/cmds/splice.cc | 2 +-
passes/cmds/splitnets.cc | 61 +-
passes/cmds/stat.cc | 70 +-
passes/cmds/torder.cc | 123 ++++
passes/equiv/Makefile.inc | 3 +
passes/equiv/equiv_add.cc | 152 +++-
passes/equiv/equiv_induct.cc | 8 +-
passes/equiv/equiv_make.cc | 2 +-
passes/equiv/equiv_mark.cc | 239 ++++++
passes/equiv/equiv_miter.cc | 2 +-
passes/equiv/equiv_purge.cc | 210 ++++++
passes/equiv/equiv_simple.cc | 6 +-
passes/equiv/equiv_struct.cc | 367 ++++++++++
passes/fsm/fsm_opt.cc | 2 +-
passes/fsm/fsm_recode.cc | 2 +-
passes/fsm/fsmdata.h | 2 +-
passes/hierarchy/Makefile.inc | 1 +
passes/hierarchy/hierarchy.cc | 10 +-
passes/hierarchy/singleton.cc | 101 +++
passes/hierarchy/submod.cc | 41 +-
passes/memory/memory_bram.cc | 10 +-
passes/memory/memory_collect.cc | 2 +-
passes/memory/memory_dff.cc | 15 +-
passes/memory/memory_share.cc | 2 +-
passes/opt/opt_clean.cc | 2 +-
passes/opt/opt_const.cc | 2 +-
passes/opt/opt_muxtree.cc | 2 +-
passes/opt/share.cc | 58 +-
passes/opt/wreduce.cc | 59 +-
passes/proc/proc_mux.cc | 189 ++++-
passes/sat/eval.cc | 2 +-
passes/sat/expose.cc | 20 +-
passes/sat/freduce.cc | 2 +-
passes/sat/sat.cc | 12 +-
passes/techmap/Makefile.inc | 3 +-
passes/techmap/abc.cc | 111 ++-
passes/techmap/alumacc.cc | 6 +-
passes/techmap/dffinit.cc | 6 +-
passes/techmap/dfflibmap.cc | 76 +-
passes/techmap/dffsr2dff.cc | 213 ++++++
passes/techmap/extract.cc | 4 +-
passes/techmap/maccmap.cc | 2 +-
passes/techmap/muxcover.cc | 6 +-
passes/techmap/simplemap.cc | 4 +-
passes/techmap/techmap.cc | 4 +-
passes/tests/test_cell.cc | 2 +-
techlibs/common/.gitignore | 2 +
techlibs/common/Makefile.inc | 16 +
techlibs/common/cellhelp.py | 34 +
techlibs/common/{synth.cc => prep.cc} | 106 +--
techlibs/common/simcells.v | 809 +++++++++++++++++++--
techlibs/common/synth.cc | 2 +
techlibs/ice40/Makefile.inc | 1 +
techlibs/ice40/brams_map.v | 16 +-
techlibs/ice40/cells_sim.v | 16 +-
techlibs/ice40/ice40_ffinit.cc | 163 +++++
techlibs/ice40/ice40_opt.cc | 21 +-
techlibs/ice40/synth_ice40.cc | 18 +
techlibs/xilinx/synth_xilinx.cc | 6 +-
tests/simple/graphtest.v | 34 +
tests/simple/memory.v | 15 +
tests/simple/task_func.v | 42 +-
tests/simple/wreduce.v | 9 +
137 files changed, 5281 insertions(+), 823 deletions(-)
create mode 100644 CodeOfConduct
create mode 100644 backends/smt2/example.v
create mode 100644 backends/smt2/example.ys
create mode 100644 backends/smt2/smtbmc.py
create mode 100644 backends/smt2/smtio.py
create mode 100644 debian/man/.gitignore
create mode 100755 debian/man/genmanpages.sh
create mode 100644 debian/man/yosys-smtbmc.txt
create mode 100644 debian/patches/spelling-fixes.patch
rename {techlibs/xilinx/example_basys3 => examples/basys3}/README (78%)
rename {techlibs/xilinx/example_basys3 => examples/basys3}/example.v (100%)
rename {techlibs/xilinx/example_basys3 => examples/basys3}/example.xdc (100%)
rename {techlibs/xilinx/example_basys3 => examples/basys3}/run.sh (100%)
rename {techlibs/xilinx/example_basys3 => examples/basys3}/run_prog.tcl (100%)
rename {techlibs/xilinx/example_basys3 => examples/basys3}/run_vivado.tcl (100%)
rename {techlibs/xilinx/example_basys3 => examples/basys3}/run_yosys.ys (100%)
rename {techlibs => examples}/cmos/cmos_cells.lib (100%)
rename {techlibs => examples}/cmos/cmos_cells.sp (100%)
rename {techlibs => examples}/cmos/cmos_cells.v (100%)
rename {techlibs => examples}/cmos/counter.v (100%)
rename {techlibs => examples}/cmos/counter.ys (100%)
rename {techlibs => examples}/cmos/testbench.sh (100%)
rename {techlibs => examples}/cmos/testbench.sp (100%)
rename misc/example.cc => examples/cxx-api/demomain.cc (83%)
create mode 100644 passes/cmds/torder.cc
create mode 100644 passes/equiv/equiv_mark.cc
create mode 100644 passes/equiv/equiv_purge.cc
create mode 100644 passes/equiv/equiv_struct.cc
create mode 100644 passes/hierarchy/singleton.cc
create mode 100644 passes/techmap/dffsr2dff.cc
create mode 100644 techlibs/common/.gitignore
create mode 100644 techlibs/common/cellhelp.py
copy techlibs/common/{synth.cc => prep.cc} (60%)
create mode 100644 techlibs/ice40/ice40_ffinit.cc
create mode 100644 tests/simple/graphtest.v
create mode 100644 tests/simple/wreduce.v
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